Memory preset adjustment based on adaptive calibration

Patent metadata

Field	Value
Publication number	US-10679698-B2
Application number	US-201815939026-A
Country	US
Kind code	B2
Filing date	Mar 28, 2018
Priority date	Mar 28, 2018
Publication date	Jun 9, 2020
Grant date	Jun 9, 2020

Abstract

A memory device includes a memory array having multiple nonvolatile memory cells that stores data as a set or a reset state of the memory cells. The nonvolatile memory cells can be resistance-based memory, which stores data based on resistive state of the memory cells. A controller coupled to the memory array periodically samples set and reset margins for memory cells of the memory array. Responsive to detection of a change in a margin, the system can adaptively adjust a preset electrical setting used to differentiate between a set state and a reset state.

First claim

What is claimed is:

1. A memory device, comprising:
a memory array having multiple nonvolatile memory cells that store data as either a set or a reset state of the memory cells; and
a controller coupled to the memory array, the controller to periodically sample set and reset margins for memory cells of the memory array, and in response to detection of a change in a margin, to adaptively adjust a preset access setting used to differentiate between a set state and a reset state for a memory cell;
wherein detection of the change in the margin includes either detection of a read retry rate higher than a retry rate threshold or detection of a number of bit errors greater than a bit error threshold.

2. The memory device of claim 1 , wherein the nonvolatile memory cells comprise memory cells that store data based on a resistive state.

3. The memory device of claim 2 , wherein the nonvolatile memory cells comprise cells of a three-dimensional crosspoint memory array.

4. The memory device of claim 1 , wherein the preset access setting comprises a trim value of an electrical setting for a voltage attribute, or a current attribute, or a timing attribute.

5. The memory device of claim 4 , wherein the electrical setting comprises a voltage trim for a read voltage.

6. The memory device of claim 5 , wherein the voltage trim for the read voltage comprises a voltage trim for a demarcation voltage (Vdm).

7. The memory device of claim 4 , wherein the electrical setting comprises a trim value for a write current.

8. The memory device of claim 1 , wherein the memory array comprises a first memory array of a first memory die, and further comprising a second memory array of a second memory die, wherein the controller is to adaptively adjust preset electrical settings independent for the first memory die and the second memory die.

9. A system comprising:
a system memory bus;
a volatile memory device coupled to the system memory bus to provide byte-addressable random access to volatile memory media; and
a nonvolatile memory device coupled to the system memory bus to provide byte-addressable random access to nonvolatile memory media, the nonvolatile memory device including:
a memory array having multiple nonvolatile memory cells that store data as either a set or a reset state of the nonvolatile memory cells; and
a controller coupled to the memory array, the controller to periodically sample set and reset margins for nonvolatile memory cells of the memory array, and in response to detection of a change in a margin, to adaptively adjust a preset access setting used to differentiate between a set state and a reset state for a nonvolatile memory cell;
wherein detection of the change in the margin includes either detection of a read retry rate higher than a retry rate threshold or detection of a number of bit errors greater than a bit error threshold.

10. The system of claim 9 , wherein the nonvolatile memory cells comprise memory cells that store data based on a resistive state.

11. The system of claim 10 , wherein the multiple nonvolatile memory cells comprise cells of a three-dimensional crosspoint memory array.

12. The system of claim 9 , wherein the preset access setting comprises a trim value of an electrical setting for a voltage attribute, or a current attribute, or a timing attribute.

13. The system of claim 12 , wherein the electrical setting comprises a voltage trim for a read voltage.

14. The system of claim 13 , wherein the voltage trim for the read voltage comprises a voltage trim for a demarcation voltage (Vdm).

15. The system of claim 12 , wherein the electrical setting comprises a trim value for a write current.

16. The system of claim 9 , wherein the memory array comprises a first memory array of a first memory die, and further comprising a second memory array of a second memory die, wherein the controller is to adaptively adjust preset electrical settings independent for the first memory die and the second memory die.

17. The system of claim 9 , further comprising:
a host processor device coupled to the system memory bus;
a memory controller coupled to the volatile memory device and the nonvolatile memory device over the system memory bus;
a display communicatively coupled to a host processor;
a network interface communicatively coupled to a host processor; or
a battery to power the system.

18. A method for adjusting margin in a memory, comprising:
periodically sampling set and reset margins for nonvolatile memory cells of a memory array having multiple memory cells that store data as either a set or a reset state of the memory cells; and
adaptively adjusting a preset setting used to differentiate between a set state and a reset state for a memory cell in response to detecting a change in a margin, wherein detecting the change in the margin comprises detecting a read retry rate higher than a retry rate threshold or detecting a number of bit errors greater than a bit error threshold.

19. The method of claim 18 , wherein the nonvolatile memory cells comprise memory cells that store data based on a resistive state.

20. The method of claim 18 , wherein the preset setting comprises a voltage trim for a demarcation voltage (Vdm), a trim value for a current setting, or a trim value for a timing setting.

21. A memory controller comprising:
a hardware interface to couple to a memory device having multiple nonvolatile memory cells that store data as either a set or a reset state of the memory cells;
control logic to periodically cause the memory device to sample set and reset margins for memory cells of the memory device, and in response to detection of a change in a margin, to adaptively adjust a preset access setting used to differentiate between a set state and a reset state for a memory cell;
wherein the control logic is to cause the memory device to sample set and reset margins in response to detection of a read retry rate higher than a retry rate threshold, or in response to detection of a number of bit errors greater than a bit error threshold; and
a register to store one or more preset access settings for the hardware interface to apply in a subsequent access to the memory controller.

22. The memory controller of claim 21 , wherein the preset access setting comprises a trim value of an electrical setting for a voltage attribute, or a current attribute, or a timing attribute.

23. The memory controller of claim 21 , wherein the memory device comprises a first of multiple memory devices, wherein the control logic is to periodically cause the first memory device to sample set and reset margins for memory cells of the first memory device, and to periodically cause a second of the multiple memory devices to sample set and reset margins for memory cells of the second memory device.

Assignees

• Intel Corp

Inventors

• Damle Prashant S
• Fang Wei
• Fazio Albert

Classifications

• G11C13/0004

  comprising amorphous/crystalline phase transition cells · CPC title

• G11C29/50

  Marginal testing, e.g. race, voltage or current testing · CPC title

• G11C13/0035

  Evaluating degradation, retention or wearout, e.g. by counting writing cycles · CPC title

• G11C13/004 Primary

  Reading or sensing circuits or methods · CPC title

• G11C2029/0409

  Online test · CPC title