Methods of operating a nonvolatile memory device and the nonvolatile memory device thereof

Patent metadata

Field	Value
Publication number	US-10332607-B2
Application number	US-201715830679-A
Country	US
Kind code	B2
Filing date	Dec 4, 2017
Priority date	Mar 13, 2017
Publication date	Jun 25, 2019
Grant date	Jun 25, 2019

Abstract

In a method of operating a nonvolatile memory device including a memory cell array, where the memory cell array includes a plurality of pages, and each of the plurality of pages includes a plurality of nonvolatile memory cells, a first sampling read operation is performed to count a first number of memory cells in a first region of a first page selected from the plurality of pages, using a first default read voltage and a first offset read voltage, and a second sampling read operation is selectively performed to count a second number of memory cells in a second region of the first page, using the first default read voltage and a second offset read voltage, based on a comparison result of the first number and a first reference value. The second offset read voltage is different from the first offset read voltage.

First claim

What is claimed is:

1. A method of operating a nonvolatile memory device including a memory cell array, wherein the memory cell array includes a plurality of pages, each of the plurality of pages includes a plurality of nonvolatile memory cells, each of the plurality of nonvolatile memory cells is configured to store a plurality of data bits, and the plurality of data bits are distinguished from one another by different threshold voltages, the method comprising:
performing a first sampling read operation to count a first number of memory cells in a first region of a first page selected from the plurality of pages, using a first default read voltage and a first offset read voltage, in response to a command and an address received from a memory controller; and
performing, selectively, a second sampling read operation to count a second number of memory cells in a second region of the first page, using the first default read voltage and a second offset read voltage, based on a comparison result of the first number and a first reference value,
wherein the second offset read voltage is different from the first offset read voltage, and
wherein performing the first sampling read operation comprises:
latching first data to a page buffer circuit coupled to the memory cell array, wherein the first data is sensed by applying the first offset read voltage to a first word-line coupled to the first page;
latching second data to the page buffer circuit, wherein the second data is sensed by applying the first default read voltage to the first word-line;
performing an exclusive OR operation on the first data and the second data to generate a first operation data which indicates a match between corresponding bits of the first data and the second data; and
counting a number of first bits in the first operation data to provide the first number.

2. The method of claim 1 , wherein the first default read voltage is a read reference voltage to distinguish a first data state from a second data state that is adjacent to the first data state, and the first and second data states are programmed to have different threshold voltage distribution.

3. The method of claim 2 , wherein the page buffer circuit includes a plurality of page buffers coupled to the memory cell array through a plurality of bit-lines,
each of the plurality of page buffers includes a sensing latch, a first data latch, a second data latch, and a third data latch which are connected in parallel with a corresponding one of the plurality of bit-lines at a sensing node,
the first data is latched to the first data latch of each of the plurality of page buffers via the sensing latch of each of the plurality of page buffers, and
the second data is latched to the second data latch of each of the plurality of page buffers via the sensing latch of each of the plurality of page buffers.

4. The method of claim 1 , wherein performing, selectively, the second sampling read operation comprises:
comparing the first number and the first reference value; and
outputting data read using the first default read voltage as output data when the first number is smaller than the first reference value.

5. The method of claim 4 , wherein when the first number is greater than or equal to the first reference value, the method further comprises:
counting the second number of memory cells to compare the first number and the second number; and
determining whether the first number or the second number is less than a third reference value,
wherein the third reference value is greater than the first reference value.

6. The method of claim 5 , wherein when the first number or the second number is smaller than the third reference value, the method further comprises:
determining whether an absolute value of a difference between the first number and the second number is smaller than a second reference value;
outputting data read using the first default read voltage as the output data when the absolute value of the difference between the first number and the second number is smaller than the second reference value;
outputting data read using the second offset read voltage as the output data when the absolute value of the difference between the first number and the second number is smaller than the second reference value, and the first number is smaller than the second number; and
outputting data read using the first offset read voltage as the output data when the absolute value of the difference between the first number and the second number is greater than or equal to the second reference value,
wherein the second reference value is greater than the first reference value and smaller than the third reference value.

7. The method of claim 5 , wherein when the first number or the second number is greater than or equal to the third reference value, the method further comprises:
determining whether the second number is greater than the first number.

8. The method of claim 7 , wherein the method further comprises:
performing a read retry operation on the first page using the first offset read voltage when the second number is greater than the first number; and
performing the read retry operation on the first page using the second offset read voltage when the second number is smaller than or equal to the first number.

9. The method of claim 5 , wherein counting the second number of memory cells comprises:
latching third data to the page buffer circuit coupled to the memory cell array, wherein the third data is sensed by applying the first default read voltage to the first word-line coupled to the first page;
latching fourth data to the page buffer circuit, wherein the fourth data is sensed by applying the second offset read voltage to the first word-line;
performing an exclusive OR operation on the third data and the fourth data to generate a second operation data which indicates a match between corresponding bits of the third data and the fourth data: and
counting a number of first bits in the second operation data to provide the second number.

10. The method of claim 1 ,
wherein a level of the first offset read voltage is smaller than a level of the first default read voltage and a level of the second offset read voltage is greater than the level of the first default read voltage,
wherein the memory cell array comprises:
first memory cells coupled to the first word-line; and
second memory cells coupled to a second word-line and stacked on the first memory cells, and
wherein at least one of the level of the first default read voltage, the level of the first offset read voltage, and the level of the second offset read voltage varies with respect to the first word-line and the second word-line.

11. The method of claim 1 , wherein the first region is defined by the first default read voltage and the first offset read voltage, and
the second region is defined by the first default read voltage and the second offset read voltage.

12. The method of claim 1 , wherein each of the plurality of nonvolatile memory cells is configured to store the plurality of data bits as one of a plurality of threshold voltage distributions corresponding to a plurality of logic states.

13. A nonvolatile memory device, comprising:
a memory cell array including a plurality of pages, wherein each of the plurality of pages includes a plurality of nonvolatile memory cells, each of the plurality of nonvolatile memory cells stores a plurality of data bits, and the plurality of data bits are distinguished from one another by different threshold voltages;
a page buffer circuit coupled to the memory cell array through a plurality of bit-lines;
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Assignees

• Samsung Electronics Co Ltd

Inventors

• Choi Na-Young
• Park Il-Han
• Song Seung-Hwan

Classifications

• G11C16/3427

  Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written · CPC title

• G11C2211/5642

  Multilevel memory with buffers, latches, registers at input or output · CPC title

• G11C11/5642

  Sensing or reading circuits; Data output circuits · CPC title

• G11C16/24

  Bit-line control circuits · CPC title

• G11C16/28

  using differential sensing or reference cells, e.g. dummy cells · CPC title