Memory device including a circuit for detecting word line defect and operating method thereof

Patent metadata

Field	Value
Publication number	US-10854250-B2
Application number	US-201815997964-A
Country	US
Kind code	B2
Filing date	Jun 5, 2018
Priority date	Oct 26, 2017
Publication date	Dec 1, 2020
Grant date	Dec 1, 2020

Abstract

A memory device comprises a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell; a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line; and a word line defect detection circuit configured to monitor a number of pulses of a pumping clock signal while applying a first voltage to the first word line to detect a defect of the first word line. The voltage generator is configured to apply a second voltage different from the first voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value.

First claim

What is claimed is:

1. A memory device comprising:
a memory cell array including a first memory cell disposed on a substrate and a second memory cell above the first memory cell;
a first word line connected to the first memory cell and a second word line connected to the second memory cell, the second word line disposed above the first word line;
a clock generator configured to generate a pumping clock signal when a pumping voltage is lower than a reference pumping voltage;
a voltage generator configured to generate the pumping voltage responsive to the pumping clock signal, and generate a first voltage based on the pumping voltage and a second voltage different from the first voltage; and
a word line defect detection circuit configured to monitor a number of pulses of the pumping clock signal while applying the first voltage to the first word line to detect a defect of the first word line,
wherein the voltage generator is configured to apply the second voltage to the second word line for programming the second memory cell when the number of pulses of the pumping clock signal is smaller than a reference value, and
wherein the voltage generator is configured to apply the second voltage to the first word line for programming the first memory cell after the programming of the second memory cell is completed.

2. The memory device of claim 1 , wherein the first voltage is smaller than the second voltage.

3. The memory device of claim 1 , wherein the first word line comprises a third word line and a fourth word line disposed above the third word line,
wherein the second word line comprises a fifth word line and a sixth word line disposed above the fifth word line, and
wherein a first interval between the third word line and the fourth word line is different from a second interval between the fifth word line and the sixth word line.

4. The memory device of claim 3 , wherein the first interval is smaller than the second interval.

5. The memory device of claim 1 , wherein the word line defect detection circuit comprises:
a counter configured to count the number of pulses of the pumping clock signal; and
a comparator configured to compare the number of pulses of the pumping clock signal with the reference value to determine whether a defect of the first word line is present or absent.

6. The memory device of claim 1 , wherein the voltage generator comprises:
a determination signal generator configured to compare the pumping voltage with a reference pumping voltage to output a determination signal,
wherein the clock generator is configured to generate the pumping clock signal based on the determination signal and a system clock signal.

7. The memory device of claim 1 , wherein the word line defect detection circuit is configured to monitor the number of pulses of the pumping clock signal after an erasing operation of a memory block including the first and second memory cells is completed.

8. A method for operating a memory device, the method comprising:
providing a memory cell array including a first memory cell disposed on a substrate, a first word line connected to the first memory cell, a second memory cell disposed above the first memory cell, and a second word line disposed above the first word line and connected to the second memory cell;
generating a pumping clock signal when a pumping voltage is lower than a reference pumping voltage;
generating the pumping voltage responsive to the pumping clock signal, a first voltage based on the pumping voltage, and a second voltage different from the first voltage;
detecting a defect of the first word line by monitoring a first number of pulses of the pumping clock signal while applying the first voltage to the first word line;
when the first number of pulses of the pumping clock signal is smaller than a first reference value, programming the second memory cell by applying the second voltage to the second word line, and
applying the second voltage to the first word line for programming the first memory cell after the programming of the second memory cell is completed.

9. The method of claim 8 , further comprising:
performing an erasing operation of a memory block including the first and second memory cells before detecting the defect of the first word line,
wherein, when the erasing operation of the memory block is failed, an operation of detecting the defect of the first word line is not executed, and when the erasing operation of the memory block is passed, the operation of detecting the defect of the first word line is executed.

10. The method of claim 8 , wherein the second voltage is greater than the first voltage.

11. The method of claim 8 , wherein the programming of the second memory cell comprises:
monitoring a second number of pulses of the pumping clock signal while applying the second voltage to the second word line to detect a defect of the second word line.

12. The method of claim 11 , wherein the programming of the second memory cell further comprises:
stopping the program operation of the second memory cell when the second number of pulses of the pumping clock signal is greater than or equal to a second reference value.

13. A memory device comprising:
a memory cell array including a first memory cell disposed on a substrate, a second memory cell disposed above the first memory cell, and a third memory cell disposed above the second memory cell;
a first word line connected to the first memory cell, a second word line connected to the second memory cell, and a third word line connected to the third memory cell, the second word line disposed above the first word line, the third word line disposed above the second word line;
a clock generator configured to generate a pumping clock signal when a pumping voltage is lower than a reference pumping voltage;
a voltage generator configured to generate the pumping voltage responsive to the pumping clock signal, and generate a first program voltage based on the pumping voltage and a second program voltage different from the first program voltage; and
a word line defect detection circuit configured to monitor a first number of pulses of the pumping clock signal while applying the first program voltage to the first word line to detect a defect of the first word line,
wherein, when the first number of pulses of the pumping clock signal is smaller than a first reference value, the word line defect detection circuit is configured to monitor a second number of pulses of the pumping clock signal while applying the first program voltage to the second word line to detect a defect of the second word line, and
wherein the voltage generator is configured to apply the second program voltage to the third word line for programming the third memory cell when the second number of pulses of the pumping clock signal is smaller than the first reference value.

14. The memory device of claim 13 , wherein the voltage generator is configured to apply the second program voltage to the second word line for programming the second memory cell after the programming of the third memory cell is completed.

15. The memory device of claim 13 , wherein, when the first number of pulses of the pumping clock signal is greater than or equal to the first reference value, the memory device is configured such that a memory block including the first to third memory cells is designated as a bad block.

16. The memory device of claim 13 , wherein the word line defect detection circuit is configured to monitor a third number of pulses of the pumping clock signal while applying the second program voltage to the third w

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jae-Yun
• Kwon Joon Soo
• Kim Byung Soo
• Kim Su-Yong
• Park Sang-Soo
• Park Il Han
• Lee Kang-Bin
• Lee Jong-Hoon
• Choi Na-Young

Classifications

• G11C29/025 Primary

  in signal lines · CPC title

• G11C16/14

  Circuits for erasing electrically, e.g. erase voltage switching circuits · CPC title

• G11C5/145 Primary

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title

• G11C16/3445

  Circuits or methods to verify correct erasure of nonvolatile memory cells · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title