Capping structure to reduce dark current in image sensors
US-12272716-B2 · Apr 8, 2025 · US
This page is not indexed by search engines while we improve data quality.
Chen Eugene patents
Chen Eugene is listed as an inventor on 19 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Chen Eugene |
| Total patents | 19 |
| First publication | Nov 20, 2018 |
| Latest publication | Apr 8, 2025 |
Notable patents
Publications ranked by popularity score, then publication date.
Capping structure to reduce dark current in image sensors
US-2024379724-A1 · Nov 14, 2024 · US
Carrier structure for etch-back silicon-on-insulator process
US-2024355902-A1 · Oct 24, 2024 · US
Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer
US-12074036-B2 · Aug 27, 2024 · US
Capping structure to reduce dark current in image sensors
US-11824077-B2 · Nov 21, 2023 · US
Capping structure to reduce dark current in image sensors
US-2023361148-A1 · Nov 9, 2023 · US
Multi-layered polysilicon and oxygen-doped polysilicon design for rf soi trap-rich poly layer
US-2022059364-A1 · Feb 24, 2022 · US
Multi-layered polysilicon and oxygen-doped polysilicon design for RF SOI trap-rich poly layer
US-11171015-B2 · Nov 9, 2021 · US
Double etch stop layer to protect semiconductor device layers from wet chemical etch
US-11164844-B2 · Nov 2, 2021 · US
Structures for bonding a group III-V device to a substrate by stacked conductive bumps
US-11158593-B2 · Oct 26, 2021 · US
Recent patents
Latest publications not already listed above.
Double etch stop layer to protect semiconductor device layers from wet chemical etch
US-2021082866-A1 · Mar 18, 2021 · US
Multi-layered polysilicon and oxygen-doped polysilicon design for rf soi trap-rich poly layer
US-2021074551-A1 · Mar 11, 2021 · US
Capping structure to reduce dark current in image sensors
US-2021074755-A1 · Mar 11, 2021 · US
Capping structure to reduce dark current in image sensors
US-10861896-B2 · Dec 8, 2020 · US
Structures for bonding a group iii-v device to a substrate by stacked conductive bumps
US-2020227369-A1 · Jul 16, 2020 · US
Structures for bonding a group III-V device to a substrate by stacked conductive bumps
US-10643964-B2 · May 5, 2020 · US
Capping structure to reduce dark current in image sensors
US-2020035741-A1 · Jan 30, 2020 · US
Structures for bonding a group iii-v device to a substrate
US-2020006271-A1 · Jan 2, 2020 · US
Wafer to wafer bonding techniques for III-V wafers and CMOS wafers
US-10134945-B1 · Nov 20, 2018 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Taiwan Semiconductor Mfg Co Ltd | 20 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H10F39/189 | 7 |
| H10F39/805 | 7 |
| H10F39/024 | 7 |
| H10F39/811 | 7 |
| H10F39/018 | 7 |