Wafer to wafer bonding techniques for III-V wafers and CMOS wafers

Patent metadata

Field	Value
Publication number	US-10134945-B1
Application number	US-201715688200-A
Country	US
Kind code	B1
Filing date	Aug 28, 2017
Priority date	Aug 28, 2017
Publication date	Nov 20, 2018
Grant date	Nov 20, 2018

Abstract

A method for wafer to wafer bonding for III-V and CMOS wafers is provided. A silicon carrier wafer is provided having an epitaxial III-V semiconductor region and an oxide region disposed over the wafer top surface, the regions having substantially equal heights. A sidewall of the epitaxial III-V semiconductor region directly contacts a sidewall of the oxide region. A eutectic bonding layer is formed over a top surface of the epitaxial III-V semiconductor region and the oxide region for bonding to the CMOS wafer which contains semiconductor devices. The silicon carrier wafer is removed, and the CMOS wafer is singulated to form a plurality of three-dimensional integrated circuits, each including a CMOS substrate corresponding to a portion of the CMOS wafer and a III-V optical device corresponding to a portion of the III-V epitaxial semiconductor region.

First claim

What is claimed is:

1. A method comprising:
providing a silicon carrier wafer having a first face and a second face, wherein an epitaxial III-V semiconductor region and an oxide region are disposed on the first face and have substantially equal heights as measured from the first face of the silicon carrier wafer, and wherein a sidewall of the epitaxial III-V semiconductor region contacts a sidewall of the oxide region;
forming a eutectic bonding layer over a top surface of the epitaxial III-V semiconductor region and the oxide region;
bonding a CMOS wafer to the eutectic bonding layer;
removing the silicon carrier wafer after the bonding of the CMOS wafer to the eutectic bonding layer; and
singulating the CMOS wafer to form a plurality of three-dimensional integrated circuits (3DICs), wherein each 3DIC includes a CMOS substrate corresponding to a portion of the CMOS wafer and a semiconductor pillar corresponding to a portion of the epitaxial III-V semiconductor region.

2. The method of claim 1 , wherein providing the silicon carrier wafer comprises:
growing an oxide layer over the first face of the silicon carrier wafer, wherein the oxide layer comprises a first oxide layer height as measured from the first face of the silicon carrier wafer;
selectively patterning and etching the oxide layer to establish an oxide region and trenches extending to an upper surface of the silicon carrier wafer, wherein the trenches create exposed regions on the upper surface of the silicon carrier wafer, and wherein the trenches form sidewalls of the oxide region;
selectively growing an epitaxial III-V semiconductor layer on the exposed regions, wherein the epitaxial III-V semiconductor layer corresponds to the III-V semiconductor region and spans a width of the trenches and is at least partially in contact with the sidewall of the oxide region, and wherein a mid-span height of the epitaxial III-V semiconductor layer is substantially equal to the first oxide layer height.

3. The method of claim 2 , wherein the growing of the epitaxial III-V semiconductor layer forms a lower EPI sidewall having a first height as measured from the first face of the silicon carrier wafer and wherein the lower EPI sidewall is in contact with the sidewall of the oxide region, and an upper EPI sidewall having a second height that extends from the first height to a mid-span height of the epitaxial III-V semiconductor layer, and wherein the upper EPI sidewall is spaced from the sidewall of the oxide layer.

4. The method of claim 3 , wherein the upper EPI sidewall has top corners that border the sidewalls of the oxide region, and wherein the top corners have a cross-sectional profile that is rounded, angled, or faceted.

5. The method of claim 1 , wherein the CMOS wafer comprises:
a monocrystalline silicon substrate comprising semiconductor devices;
interconnect layers disposed above the monocrystalline silicon substrate and electrically coupled to the semiconductor devices;
contacts disposed above the interconnect layers and electrically coupled to the interconnect layers;
a conductive layer disposed above and electrically coupled to the contacts; and
an adhesive bonding layer disposed above and in direct contact with the conductive layer.

6. The method of claim 5 , wherein after the removing of the silicon carrier wafer,
selectively patterning and etching the epitaxial III-V semiconductor region to form trenches extending to an upper surface of the eutectic bonding layer, wherein the trenches define spaced apart III-V semiconductor pillars with mesa top surfaces and with mesa sidewalls, and wherein the trenches expose open regions on an upper surface of the eutectic bonding layer and adjacent to the III-V semiconductor pillars;
forming a conformal coating on the mesa top surfaces, the mesa sidewalls, and the open regions; and
subjecting the conformal coating to a vertical etch-back process preferentially removing the conformal coating from the mesa top surfaces and the open regions to leave spacers covering a sidewall of III-V semiconductor pillars.

7. The method of claim 6 wherein the forming of the 3DICs comprises forming conductive pads and vias comprising:
forming conductive pads on the mesa top surfaces, wherein a conductive pad comprises a top surface and a conductive pad height as measured from a top surface of the conductive layer;
vertically etching through the eutectic bonding layer and the adhesive bonding layer and stopping at an upper surface of the conductive layer, and leaving spaced apart pedestals of the eutectic bonding layer and the adhesive bonding layer directly beneath the III-V semiconductor pillars;
forming a via mask and etching the via mask to form via trenches spaced apart from and between the III-V semiconductor pillars and positioned above a vertical projection of a top surface of the contacts, and extending down to the upper surface of the conductive layer, and extending up to a via trench height that exceeds the conductive pad height;
depositing metal to fill the via trenches and to form vias electrically coupled to the conductive layer; and
performing a CMP process to a via height, wherein the via height that is less than the via trench height and greater than the conductive pad height.

8. The method of claim 7 , wherein the conductive pad has a smaller surface area than a surface area of the mesa top surface.

9. The method of claim 8 wherein forming of the 3DICs comprises forming a redistribution layer comprising:
vertically etching through the conductive layer and stopping at an upper surface of the CMOS wafer, to electrically isolate the vias from adjacent regions of the conductive layer;
forming a protective layer that fills between neighboring III-V semiconductor pillars and vias and extends to a height that exceeds the conductive pad height;
forming a second mask over the protective layer, and with the second mask in place etching the protective layer to form vertical connection trenches that expose the top surface of the conductive pads, and to form horizontal connection trenches that connect the vertical trenches to the vias, wherein the horizontal connection trenches comprise an upper surface height and a lower surface height;
depositing metal to fill the vertical and horizontal connecting trenches, and performing a CMP process to a height that is between the upper and lower surface heights of the horizontal trench to form electrical connections between the III-V semiconductor pillars and the semiconductor devices of the CMOS wafer.

10. The method of claim 1 , wherein providing the silicon carrier wafer comprises:
growing an epitaxial III-V semiconductor layer over the first face of a silicon carrier wafer, wherein the epitaxial III-V semiconductor layer comprises an EPI layer height;
selectively patterning and etching the epitaxial III-V semiconductor layer to establish the epitaxial III-V semiconductor region and to establish trenches extending to an upper surface of the silicon carrier wafer, wherein the trenches create exposed regions on the upper surface of the silicon carrier wafer, and wherein the trenches create sidewalls of the epitaxial III-V semiconductor region; and
selectively growing an oxide layer on the exposed regions, wherein the oxide layer corresponds to the oxide region and spans a width of the trenches and is at least partially in contact with the sidewall of the epitaxial III-V semiconductor region, and wherein a mid-span height of the oxide layer is substantially equal to the EPI layer height.

11. The method of claim 2 , wherein prior to forming of the eutectic bonding layer, a second oxide layer is deposited or grown above the oxide region and

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Liu Ming Chyi
• Yu Chen-Hua
• Tsai Chia-Shiung
• Kalnitsky Alexander
• Lee Ru-Liang
• Chen Eugene

Classifications

• H10W10/181

  Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers · CPC title

• H10P90/1914

  using bonding · CPC title

• H10P10/12 Primary

  Bonding of semiconductor wafers or semiconductor substrates to semiconductor wafers or semiconductor substrates (preparing SOI wafers using bonding H10P90/1914) · CPC title

• H10D64/0116

  to Group III-V semiconductors · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title