Structures for bonding a group III-V device to a substrate by stacked conductive bumps

Patent metadata

Field	Value
Publication number	US-11158593-B2
Application number	US-202016829267-A
Country	US
Kind code	B2
Filing date	Mar 25, 2020
Priority date	Jul 2, 2018
Publication date	Oct 26, 2021
Grant date	Oct 26, 2021

Abstract

Various embodiments of the present application are directed towards a method for forming an integrated chip in which a group III-V device is bonded to a substrate, as well as the resulting integrated chip. In some embodiments, the method includes: forming a chip including an epitaxial stack, a metal structure on the epitaxial stack, and a diffusion layer between the metal structure and the epitaxial stack; bonding the chip to a substrate so the metal structure is between the substrate and the epitaxial stack; and performing an etch into the epitaxial stack to form a mesa structure with sidewalls spaced from sidewalls of the diffusion layer. The metal structure may, for example, be a metal bump patterned before the bonding or may, for example, be a metal layer that is on an etch stop layer and that protrudes through the etch stop layer to the diffusion layer.

First claim

What is claimed is:

1. An integrated chip comprising:
a substrate;
a mesa structure overlying the substrate and comprising a semiconductor material;
a bump structure between the substrate and the mesa structure, wherein the bump structure comprises a conductive material at a top of the bump structure; and
a diffusion layer between and bordering the bump structure and the mesa structure, wherein the diffusion layer is recessed into the mesa structure and comprises the semiconductor and conductive materials, wherein a sidewall of the diffusion layer is laterally offset from a neighboring semiconductor sidewall of the mesa structure that comprises the semiconductor material, and wherein the sidewall has an edge elevated relative to a bottom edge of the neighboring semiconductor sidewall and recessed relative to a top edge of the neighboring semiconductor sidewall.

2. The integrated chip according to claim 1 , further comprising:
an etch stop layer on the mesa structure, between the mesa structure and the substrate, wherein the bump structure extends through the etch stop layer to the diffusion layer.

3. The integrated chip according to claim 2 , wherein the bump structure wraps around an adjoining corner of the etch stop layer.

4. The integrated chip according to claim 1 , wherein the mesa structure comprises a semiconductor layer within which the diffusion layer is recessed.

5. The integrated chip according to claim 1 , wherein the mesa structure comprises a first alternating stack of different group III-V layers, an active group III-V layer overlying the first alternating stack, and a second alternating stack of different group III-V layers overlying the active group III-V layer.

6. The integrated chip according to claim 1 , further comprising:
a conductive contact on the mesa structure, wherein the mesa structure is between the conductive contact and the bump structure; and
a conductive structure extending from the substrate to the conductive contact, wherein the conductive structure has a T-shaped profile.

7. The integrated chip according to claim 1 , wherein the substrate comprises:
a semiconductor substrate;
semiconductor devices on the semiconductor substrate; and
an interconnect structure covering the semiconductor substrate and the semiconductor devices.

8. The integrated chip according to claim 1 , wherein a bottom edge of the sidewall is level with the bottom edge of the neighboring semiconductor sidewall.

9. An integrated chip comprising:
a substrate;
a mesa structure overlying the substrate and comprising a semiconductor layer;
a conductive bump structure between the substrate and the mesa structure; and
a diffusion layer between the conductive bump structure and the mesa structure, wherein the diffusion layer is sunken into a bottom of the semiconductor layer and has a width less than that of the semiconductor layer at the bottom, and wherein the diffusion layer comprises a semiconductor material of the semiconductor layer and further comprises a conductive material that diffused from the conductive bump structure to the diffusion layer.

10. The integrated chip according to claim 9 , wherein the diffusion layer directly contacts the conductive bump structure at an interface, and wherein the conductive bump structure has the conductive material at the interface.

11. The integrated chip according to claim 9 , wherein the diffusion layer directly contacts the semiconductor layer at an interface, and wherein the interface has an inverted U-shaped profile.

12. The integrated chip according to claim 9 , wherein the mesa structure comprises a pair of Bragg reflectors and an active semiconductor layer that are vertically stacked with the active semiconductor layer between the Bragg reflectors.

13. The integrated chip according to claim 9 , further comprising:
an etch stop layer on the bottom of the mesa structure, wherein the conductive bump structure protrudes through the etch stop layer.

14. An integrated chip comprising:
a substrate;
a vertical-cavity surface-emitting laser (VCSEL) overlying the substrate, wherein the VCSEL comprises a semiconductor layer at a bottom surface of the VCSEL;
a bump structure between the substrate and the VCSEL, wherein the bump structure comprises a conductive material at a top surface of the bump structure; and
a diffusion layer between the bump structure and the VCSEL, wherein the diffusion layer directly contacts the top surface of the bump structure and comprises the conductive material and a semiconductor material of the semiconductor layer;
wherein the semiconductor layer wraps around a corner of the diffusion layer from a sidewall of the diffusion layer to a top surface of the diffusion layer.

15. The integrated chip according to claim 14 , wherein the diffusion layer is a region of the semiconductor layer to which the conductive material diffused and at which the conductive and semiconductor materials mixed.

16. The integrated chip according to claim 14 , wherein the top surface of the bump structure has a width-wise center aligned to a width-wise center of the diffusion layer.

17. The integrated chip according to claim 14 , wherein the conductive material comprises a semiconductor.

18. The integrated chip according to claim 14 , wherein the diffusion layer directly contacts the bottom surface of the VCSEL.

19. The integrated chip according to claim 14 , wherein the diffusion layer comprises germanium, gallium, arsenic, or any combination of the foregoing from the VCSEL, and wherein the diffusion layer further comprises nickel, gold, or any combination of the foregoing from the bump structure.

20. The integrated chip according to claim 14 , wherein the bump structure has an inverted T-shaped profile.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chen Jhih-Bin
• Tsai Chia-Shiung
• Liu Ming Chyi
• Chen Eugene

Classifications

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/29

  Bond pads specially adapted therefor · CPC title

• H10W72/952

  comprising metals or metalloids, e.g. PbSn, Ag or Cu · CPC title

• H10W72/923

  Bond pads having multiple stacked layers · CPC title