Systems and methods for mixed directory entry organization in probe filter
US-2026093631-A1 · Apr 2, 2026 · US
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Apte Amit P patents
Apte Amit P is listed as an inventor on 51 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Apte Amit P |
| Total patents | 51 |
| First publication | Oct 1, 2015 |
| Latest publication | Apr 2, 2026 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for high fidelity region from probe filter entry
US-2026086941-A1 · Mar 26, 2026 · US
Systems and methods for region-based probe filter shootdown
US-2026086950-A1 · Mar 26, 2026 · US
Shadow tag management for accelerator partitions
US-2026050554-A1 · Feb 19, 2026 · US
Systems and methods for facilitating dual ownership of cache regions
US-12499061-B2 · Dec 16, 2025 · US
Shadow tag management for accelerator partitions
US-12423241-B1 · Sep 23, 2025 · US
Coherent block read fulfillment
US-12393532-B2 · Aug 19, 2025 · US
Systems and methods for facilitating dual ownership of cache regions
US-2025245172-A1 · Jul 31, 2025 · US
Systems and methods relating to confidential computing key mixing hazard management
US-2025240156-A1 · Jul 24, 2025 · US
Systems and methods for indicating recently invalidated cache lines
US-2025217297-A1 · Jul 3, 2025 · US
Recent patents
Latest publications not already listed above.
Tiered memory caching
US-12189535-B2 · Jan 7, 2025 · US
Region based split-directory scheme to adapt to large cache sizes
US-12158845-B2 · Dec 3, 2024 · US
Probe filter directory management
US-12141066-B2 · Nov 12, 2024 · US
Zero value memory compression
US-12066944-B2 · Aug 20, 2024 · US
Systems and methods for hosting an interleave across asymmetrically populated memory channels across two or more different memory types
US-2024220405-A1 · Jul 4, 2024 · US
Tiered memory caching
US-2024220415-A1 · Jul 4, 2024 · US
Coherent block read fulfillment
US-2024202144-A1 · Jun 20, 2024 · US
Probe filter retention based low power state
US-11940858-B2 · Mar 26, 2024 · US
Coherent block read fulfillment
US-11874783-B2 · Jan 16, 2024 · US
Region based directory scheme to adapt to large cache sizes
US-11809322-B2 · Nov 7, 2023 · US
Home agent based cache transfer acceleration scheme
US-11782848-B2 · Oct 10, 2023 · US
Demand based probe filter initialization after low power state
US-11703932-B2 · Jul 18, 2023 · US
Coherent block read fulfillment
US-2023195662-A1 · Jun 22, 2023 · US
Probe filter directory management
US-2023195632-A1 · Jun 22, 2023 · US
Probe filter retention based low power state
US-2023039289-A1 · Feb 9, 2023 · US
Demand based probe filter initialization after low power state
US-2022413586-A1 · Dec 29, 2022 · US
Probe filter retention based low power state
US-11487340-B1 · Nov 1, 2022 · US
Region based split-directory scheme to adapt to large cache sizes
US-2022237117-A1 · Jul 28, 2022 · US
Region based split-directory scheme to adapt to large cache sizes
US-11314646-B2 · Apr 26, 2022 · US
Region based directory scheme to adapt to large cache sizes
US-2021406180-A1 · Dec 30, 2021 · US
Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Advanced Micro Devices Inc | 51 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| G06F2212/1024 | 19 |
| G06F12/0817 | 16 |
| G06F12/0833 | 15 |
| G06F12/0824 | 14 |
| G06F12/0891 | 13 |