Zero value memory compression

Patent metadata

Field	Value
Publication number	US-12066944-B2
Application number	US-201916723780-A
Country	US
Kind code	B2
Filing date	Dec 20, 2019
Priority date	Dec 20, 2019
Publication date	Aug 20, 2024
Grant date	Aug 20, 2024

Abstract

A coherency management device receives requests to read data from or write data to an address in a main memory. On a write, if the data includes zero data, an entry corresponding to the memory address is created in a cache directory if it does not already exist, is set to an invalid state, and indicates that the data includes zero data. The zero data is not written to main memory or a cache. On a read, the cache directory is checked for an entry corresponding to the memory address. If the entry exists in the cache directory, is invalid, and includes an indication that data corresponding to the memory address includes zero data, the coherency management device returns zero data in response to the request without fetching the data from main memory or a cache.

First claim

What is claimed is:

1. A coherency management device, comprising:
circuitry configured to receive a request for a non-temporal read of data stored at an address in a main memory; and
circuitry configured to, responsive to the request for a non-temporal read, and to a cache directory including a spare, unused, or invalid directory entry:
create a cache directory entry for the address using the spare, unused, or invalid directory entry,
set a state of the cache directory entry to an invalid state, wherein the invalid state indicates that no cached copies of data corresponding to the address are valid, and
set, in the cache directory entry, an indication that data corresponding to the address comprises zero data.

2. The coherency management device of claim 1 , wherein the indication comprises a bit in the cache directory entry, a spare state in a state field of the cache directory entry, a bit in a state field of the cache directory entry, and/or a bit in a sharing vector field of the cache directory entry.

3. The coherency management device of claim 1 , wherein the coherency management device is configured to return the zero data in response to the request without reading the main memory if the cache directory entry is invalid and includes the indication.

4. The coherency management device of claim 1 , wherein the coherency management device comprises a coherent slave device, probe filter device, and/or snoop filter device.

5. The coherency management device of claim 1 , wherein the coherency management device receives the request from a coherent master device.

6. The coherency management device of claim 1 , wherein the cache directory entry for the address includes sharing vector that indicates which caches contain the cached copies of data corresponding to the address.

7. A method for managing cache coherence in a computer system, the method comprising:
receiving, by a coherency management device, a request for a non-temporal read of data stored at an address in a main memory; and
in response to the request for a non-temporal read, and to a cache directory including a spare, unused, or invalid directory entry:
creating a cache directory entry for the address using the spare, unused, or invalid directory entry,
setting a state of the cache directory entry to an invalid state, wherein the invalid state indicates that no cached copies of data corresponding to the address are valid, and
setting, in the cache directory entry, an indication that data corresponding to the address comprises zero data.

8. The method of claim 7 , wherein the indication comprises a bit in the cache directory entry, a spare state in a state field of the cache directory entry, a bit in a state field of the cache directory entry, and/or a bit in a sharing vector field of the cache directory entry.

9. The method of claim 7 , wherein the coherency management device returns the zero data in response to the request without reading the main memory if the cache directory entry is invalid and includes the indication.

10. The method of claim 7 , wherein the coherency management device receives the request from a coherent master device.

11. The method of claim 7 , wherein the cache directory entry for the address includes sharing vector that indicates which caches contain the cached copies of data corresponding to the address.

12. A coherency management device comprising:
circuitry configured to receive a request for a non-temporal write to an address in a main memory; and
circuitry configured to, responsive to the request for the non-temporal write, and to determining that a cache directory includes including a spare, unused, or invalid directory entry:
create a cache directory entry for the address using the spare, unused, or invalid directory entry,
set a state of the cache directory entry to an invalid state, wherein the invalid state indicates that no cached copies of data corresponding to the address are valid, and
set, in the cache directory entry, an indication that data corresponding to the address includes zero data.

13. The coherency management device of claim 12 , wherein the data includes zero data where the data includes only zeros and/or the request includes an instruction which includes an opcode which instructs a write of zeros to the address.

14. The coherency management device of claim 12 , wherein the indication comprises at least one bit in a state field of the cache directory entry, a spare state in a state field of the cache directory entry, a bit in a state field of the cache directory entry, and/or a bit in a sharing vector field of the cache directory entry.

15. The coherency management device of claim 12 , wherein the coherency management device is configured to set the indication in response to the request without writing to the main memory if the data includes zero data.

16. The coherency management device of claim 12 , wherein the coherency management device comprises a coherent slave device, probe filter device, and/or snoop filter device.

17. The coherency management device of claim 12 , wherein the coherency management device receives the request from a coherent master device.

18. The coherency management device of claim 12 , wherein the cache directory entry for the address includes sharing vector that indicates which caches contain the cached copies of data corresponding to the address.

19. A method for managing cache coherence in a computer system, the method comprising:
receiving, by a coherency management device, a request for a non-temporal write of data to an address in a main memory; and
in response to the request for the non-temporal write, and to a cache directory including a spare, unused, or invalid directory entry:
creating a cache directory entry for the address using the spare, unused, or invalid directory entry,
setting a state of the cache directory entry to an invalid state, wherein the invalid state indicates that no cached copies of data corresponding to the address are valid, and
setting, in the cache directory entry, an indication that data corresponding to the address includes zero data.

20. The method of claim 19 , wherein the data includes zero data where the data includes only zeros and/or the request includes an instruction which includes an opcode which instructs a write of zeros to the address.

21. The method of claim 19 , wherein the indication comprises at least one bit in a state field of the cache directory entry, a spare state in a state field of the cache directory entry, a bit in a state field of the cache directory entry, and/or a bit in a sharing vector field of the cache directory entry.

22. The method of claim 19 , wherein if the data includes zero data, the coherency management device sets the indication in response to the request without writing the main memory.

23. The method of claim 19 , wherein the coherency management device comprises a coherent slave device, probe filter device, and/or snoop filter device.

24. The method of claim 19 , wherein the coherency management device receives the request from a coherent master device.

25. The method of claim 19 , wherein the cache directory entry for the address includes sharing vector that indicates which caches contain the cached copies of data corresponding to the address.

Assignees

• Advanced Micro Devices Inc

Inventors

• Kalyanasundharam Vydhyanathan
• Apte Amit P

Classifications

• G06F12/0888

  using selective caching, e.g. bypass · CPC title

• G06F12/0891

  using clearing, invalidating or resetting means · CPC title

• G06F12/0817 Primary

  using directory methods · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title

• G06F2212/1041

  Resource optimization · CPC title