Coherent block read fulfillment

Patent metadata

Field	Value
Publication number	US-11874783-B2
Application number	US-202117557639-A
Country	US
Kind code	B2
Filing date	Dec 21, 2021
Priority date	Dec 21, 2021
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

A coherent memory fabric includes a plurality of coherent master controllers and a coherent slave controller. The plurality of coherent master controllers each include a response data buffer. The coherent slave controller is coupled to the plurality of coherent master controllers. The coherent slave controller, responsive to determining a selected coherent block read command is guaranteed to have only one data response, sends a target request globally ordered message to the selected coherent master controller and transmits responsive data. The selected coherent master controller, responsive to receiving the target request globally ordered message, blocks any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

First claim

What is claimed is:

1. A coherent memory fabric comprising:
a plurality of coherent master controllers each including a response data buffer; and
a coherent slave controller coupled to the plurality of coherent master controllers, the coherent slave controller operable to, responsive to determining a selected coherent block read command from a selected coherent master controller is guaranteed to have only one data response, send a target request globally ordered message to the selected coherent master controller and transmit responsive data.

2. The coherent memory fabric of claim 1 , wherein the selected coherent master controller, responsive to the target request globally ordered message, updates an allocation in the response data buffer such that only one response data buffer entry is reserved for the selected coherent block read command.

3. The coherent memory fabric of claim 2 , wherein the selected coherent master controller is operable to, responsive to receiving the target request globally ordered message, block any coherent probes to an address associated with the selected coherent block read command until receipt of the responsive data is acknowledged by a requesting client.

4. The coherent memory fabric of claim 2 , wherein the selected coherent master controller, after updating the allocation, immediately transmits a subsequent memory access command to the coherent slave controller.

5. The coherent memory fabric of claim 1 , wherein:
the coherent slave controller further comprises a coherent slave data buffer; and
the coherent slave controller, responsive to determining a selected coherent block read command from a selected coherent master controller is guaranteed to have only one data response, de-allocates an entry of the coherent slave data buffer previously allocated for the responsive data immediately following transmitting the responsive data without requiring a source done message from the selected coherent master controller.

6. The coherent memory fabric of claim 5 , wherein:
the coherent slave controller, responsive to determining a second selected coherent block read command is not guaranteed to have only one data response, transmits a target done message to the selected coherent master controller, transmits response data to the selected coherent master controller, and de-allocates a coherent slave data buffer entry for the responsive data only after receiving a source done message from the selected coherent master controller indicating that the responsive data has been received.

7. The coherent memory fabric of claim 1 , wherein the coherent slave controller determines that the selected coherent block read command is guaranteed to have only one data response by performing a probe filter lookup in a probe filter associated with the plurality of coherent master controllers.

8. A method, comprising:
from a coherent master controller, transmitting a coherent block read command to a coherent slave controller over a coherent data fabric;
at the coherent slave controller, determining that the coherent block read command is guaranteed to have only one data response; and
at the coherent slave controller, responsive to determing the coherent block read command is guaranteed to have only one data response, sending a target request globally ordered message to the coherent master controller and transmitting responsive data.

9. The method of claim 8 , wherein the coherent master controller, responsive to the target request globally ordered message, updates an allocation in a response data buffer such that only one response data buffer entry is reserved for the coherent block read command.

10. The method of claim 9 , further comprising, at the coherent master controller, responsive to receiving the target request globally ordered message, blocking any coherent probes to an address associated with the coherent block read command until the responsive data is received.

11. The method of claim 9 , wherein the coherent master controller, after updating the allocation, immediately transmits a subsequent memory access command to the coherent slave controller.

12. The method of claim 8 , wherein the coherent slave controller, responsive to determining the coherent block read command from a selected coherent master controller is guaranteed to have only one data response, de-allocates an entry of a coherent slave data buffer previously allocated for the responsive data immediately following transmitting the responsive data without requiring a source done message from the selected coherent master controller.

13. The method of claim 8 , wherein the coherent slave controller, responsive to determining that a second coherent block read command is not guaranteed to have only one data response, transmits a target done message to the coherent master controller, transmits second response data to the coherent master controller, and de-allocates a data buffer entry for the responsive data only after receiving a source done message from the coherent master controller indicating that the second response data has been received.

14. The method of claim 8 , wherein the coherent slave controller begins transmitting the responsive data in parallel with sending the target request globally ordered message, or immediately after sending the target request globally ordered message.

15. The method of claim 8 , wherein the coherent slave controller determines that the coherent block read command is guaranteed to have only one data response by performing a probe filter lookup in a probe filter associated with a plurality of coherent master controllers.

16. A data processing system comprising:
a plurality of data processors;
a volatile memory; and
a coherent memory fabric including:
a plurality of coherent master controllers coupled to respective ones of the data processors and each including a response data buffer; and
a coherent slave controller coupled to the volatile memory over a bus, and coupled to the plurality of coherent master controllers, the coherent slave controller operable to, responsive to determining a selected coherent block read command from a selected coherent master controller is guaranteed to have only one data response, send a target request globally ordered message to the selected coherent master controller and transmit responsive data.

17. The data processing system of claim 16 , wherein the selected coherent master controller, responsive to the target request globally ordered message, updates an allocation in the response data buffer such that only one response data buffer entry is reserved for the selected coherent block read command.

18. The data processing system of claim 17 , wherein the selected coherent master controller is operable to, responsive to receiving the target request globally ordered message, block any coherent probes to an address associated with the selected coherent block read command until the responsive data is received.

19. The data processing system of claim 16 , wherein:
the coherent slave controller further comprises a coherent slave data buffer; and
the coherent slave controller, responsive to determining a selected coherent block read command from a selected coherent master controller is guaranteed to have only one data response, de-allocates an entry of the coherent slave data buffer previously allocated for the responsive data immediately following transmitting the responsive data without requiring a source done message from the selected coherent master controller.

20. The data proc

Assignees

• Advanced Micro Devices Inc

Inventors

• Kalyanasundharam Vydhyanathan
• Apte Amit P
• Morton Eric Christopher
• Balakrishnan Ganesh
• Ling Ann M

Classifications

• G06F12/0833

  in combination with broadcast means (e.g. for invalidation or updating) · CPC title

• G06F12/0831

  using a bus scheme, e.g. with bus monitoring or watching means · CPC title

• G06F2212/1024

  Latency reduction · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2213/0038

  System on Chip · CPC title