Tiered memory caching

Patent metadata

Field	Value
Publication number	US-12189535-B2
Application number	US-202218091140-A
Country	US
Kind code	B2
Filing date	Dec 29, 2022
Priority date	Dec 29, 2022
Publication date	Jan 7, 2025
Grant date	Jan 7, 2025

Abstract

The disclosed computer-implemented method includes locating, from a processor storage, a partial tag corresponding to a memory request for a line stored in a memory having a tiered memory cache and in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line. The method also includes fetching, in response to a full tag hit, the requested line from the partition of the tiered memory cache. Various other methods, systems, and computer-readable media are also disclosed.

First claim

What is claimed is:

1. A device comprising:
a physical memory comprising at least two partitions, wherein a first partition of the at least two partitions acts as a cache for a second partition of the at least two partitions; and
a controller configured to:
locate, from a processor storage, a partial tag corresponding to a memory request for a line stored in the second partition;
in response to a partial tag hit for the memory request, locate, from the first partition, a full tag for the line; and
process, based on locating the full tag, the requested line from the first partition according to the memory request.

2. The device of claim 1 , wherein the controller is further configured to, in response to a full tag miss, fetch the requested line from the second partition.

3. The device of claim 1 , wherein the controller is further configured to, in response to a partial tag miss, fetch the requested line from the second partition.

4. The device of claim 3 , wherein the controller is further configured to:
evict a page from the first partition; and
replace, in the processor storage, a partial tag corresponding to the evicted page with a partial tag corresponding to the missed partial tag.

5. The device of claim 4 , wherein the controller is further configured to write the evicted page to the second partition when the evicted page is dirty.

6. The device of claim 1 , wherein the full tag is stored using one or more error correction code (ECC) bits in the first partition.

7. The device of claim 1 , wherein the partial tag corresponds to a page.

8. The device of claim 1 , wherein the partial tag comprises a subset of the corresponding full tag.

9. The device of claim 1 , wherein the first partition comprises a set associative cache for the second partition.

10. A system comprising:
a physical memory comprising at least two partitions, wherein a first partition of the at least two partitions acts as a cache for a second partition of the at least two partitions;
at least one physical processor comprising a processor storage; and
a controller configured to:
locate, from the processor storage, a partial tag corresponding to a memory request for a line stored in the second partition;
in response to a partial tag hit for the memory request, locate, from the first partition, a full tag for the line;
in response to a full tag miss, fetch the requested line from the second partition; and
process the requested line according to the memory request.

11. The system of claim 10 , wherein the controller is further configured to:
in response to a partial tag miss, fetch the requested line from the second partition;
evict a page from the first partition; and
replace, in the processor storage, a partial tag corresponding to the evicted page with a partial tag corresponding to the missed partial tag.

12. The system of claim 11 , wherein the controller is further configured to write the evicted page to the second partition when the evicted page is dirty.

13. The system of claim 10 , wherein the full tag is stored using one or more error correction code (ECC) bits in the first partition.

14. The system of claim 10 , wherein the partial tag corresponds to a page and the partial tag comprises a subset of the corresponding full tag.

15. The system of claim 10 , wherein the first partition comprises a set associative cache for the second partition.

16. A method comprising:
locating, from a processor storage of at least one physical processor, a partial tag corresponding to a memory request for a line stored in a physical memory;
in response to a partial tag miss, fetching the requested line from the physical memory;
evicting a page from a tiered memory cache comprising a set associative cache for the physical memory; and
replacing, in the processor storage, a partial tag corresponding to the evicted page with a partial tag corresponding to the missed partial tag.

17. The method of claim 16 , further comprising writing the evicted page to the memory when the evicted page is dirty.

18. The method of claim 16 , further comprising:
in response to a partial tag hit for the memory request, locating, from a partition of the tiered memory cache indicated by the partial tag, a full tag for the line;
in response to a full tag miss, fetching the requested line from the physical memory; and
processing, based on locating the full tag in the partition of the tiered memory cache, the requested line from the partition of the tiered memory cache according to the memory request.

19. The method of claim 18 , wherein the full tag is stored using one or more error correction code (ECC) bits in the tiered memory cache.

20. The method of claim 18 , wherein the partial tag corresponds to a page and the partial tag comprises a subset of the corresponding full tag.

Assignees

• Advanced Micro Devices Inc

Inventors

• Kalyanasundharam Vydhyanathan
• Balakrishnan Ganesh
• Lepak Kevin M
• Apte Amit P

Classifications

• G06F2212/1016

  Performance improvement · CPC title

• G06F12/0897 Primary

  with two or more cache hierarchy levels (with multilevel cache hierarchies G06F12/0811) · CPC title