Gate-all-around integrated circuit structures having uniform threshold voltages and tight gate endcap tolerances

Patent metadata

Field	Value
Publication number	US-12310060-B2
Application number	US-202117357711-A
Country	US
Kind code	B2
Filing date	Jun 24, 2021
Priority date	Jun 24, 2021
Publication date	May 20, 2025
Grant date	May 20, 2025

Abstract

An integrated circuit structure comprises a first and second vertical arrangement of horizontal nanowires in a PMOS region and in an NMOS region. A first gate stack having a P-type conductive layer surrounds the first vertical arrangement of horizontal nanowires. A second gate stack surrounds the second vertical arrangement of horizontal nanowires. In one embodiment, the second gate stack has an N-type conductive layer, the P-type conductive layer is over the second gate stack, and an N-type conductive fill is between N-type conductive layer and the P-type conductive layer to provide same polarity metal filled gates. In another embodiment, the second gate stack has an N-type conductive layer comprising Titanium (Ti) and “Nitrogen (N) having a low saturation thickness of 3-3.5 nm surrounding the nanowires, and the N-type conductive layer is covered by the P-type conductive layer.

First claim

What is claimed is:

1. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires in a PMOS region;
a second vertical arrangement of horizontal nanowires in an NMOS region;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires, a second portion extending laterally spaced apart from the first portion along a sidewall of a first gate plug, a third portion extending vertically between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, and a fourth portion over a second gate stack; and
the second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires, a second portion extending vertically and laterally beside and spaced apart from the first portion along the vertical third portion of the P-type conductive layer, and a third portion extending laterally beside and spaced apart from the first portion along a sidewall of a second gate plug,
wherein the second gate stack includes an N-type conductive fill over the second gate stack and under the fourth portion of the first gate stack to provide the integrated circuit structure with same polarity filled gates.

2. The integrated circuit structure of claim 1 , wherein a P-type conductive fill is over both the first gate stack in the PMOS region and the second gate stack in the NMOS region.

3. The integrated circuit structure of claim 1 , wherein the integrated circuit structure comprises transistors that operate in saturation mode on all nanowire sides regardless of a gate endcap tolerance between 3.5 nm and 10 nm.

4. The integrated circuit structure of claim 1 , wherein the P-type conductive layer has a thickness of approximately 3.5-4 nm, which is greater than a saturation thickness of 3.5 nm for the P-type conductive layer.

5. The integrated circuit structure of claim 1 , wherein the N-type conductive layer and the N-type conductive fill are of a same material type.

6. The integrated circuit structure of claim 1 , wherein the first gate stack and the second gate stack are recessed at different levels below a gate height.

7. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires in a PMOS region;
a second vertical arrangement of horizontal nanowires in an NMOS region;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires, a second portion extending laterally spaced apart from the first portion along a sidewall of a first gate plug, a third portion extending vertically between the first vertical arrangement of horizontal nanowires and the second vertical arrangement of horizontal nanowires, and a fourth portion conformally covering a second gate stack; and
the second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer comprising Titanium (Ti) and Nitrogen (N) with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires, a second portion extending laterally beside and spaced apart from the first portion in contact with the third portion of the P-type conductive layer, and a third portion extending laterally beside and spaced apart from the first portion along a sidewall of a second gate plug.

8. The integrated circuit structure of claim 7 , wherein a P-type conductive fill is over both the first gate stack in the PMOS region and the second gate stack in the NMOS region.

9. The integrated circuit structure of claim 7 , wherein the integrated circuit structure comprises transistors that operate in saturation mode on all nanowire sides regardless of a gate endcap tolerance between 3.5 nm and 10 nm even though an opposite polarity P-type conductive layer is over the second gate stack in the NMOS region.

10. The integrated circuit structure of claim 7 , wherein the N-type conductive layer comprising Titanium (Ti) and Nitrogen (N) has a thickness of approximately 3.5-4 nm, which is greater than a saturation thickness of 3-3.5 nm for the N-type conductive layer comprising Titanium (Ti) and Nitrogen (N).

11. The integrated circuit structure of claim 7 , wherein the P-type conductive layer has a thickness of approximately 3.5-4 nm, which is greater than a saturation thickness of 3.5 nm for the P-type conductive layer.

12. An integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires in a PMOS region;
a second vertical arrangement of horizontal nanowires in an NMOS region;
a first gate stack over the first vertical arrangement of horizontal nanowires, the first gate stack having a P-type conductive layer with a first portion surrounding the nanowires of the first vertical arrangement of horizontal nanowires a second portion extending laterally spaced apart from the first portion along a sidewall of a first gate plug, a third portion conformally covering a second gate stack;
the second gate stack over the second vertical arrangement of horizontal nanowires, the second gate stack having an N-type conductive layer comprising Titanium (Ti) and Nitrogen (N) with a first portion surrounding the nanowires of the second vertical arrangement of horizontal nanowires, a second portion extending laterally beside the first portion, and a third portion extending laterally beside and spaced apart from the first portion along a sidewall of a second gate plug; and
a TiN layer extending under the second gate stack and along the sidewall of the second gate plug.

13. The integrated circuit structure of claim 12 , wherein a P-type conductive fill over both the first gate stack in the PMOS region and the second gate stack in the NMOS region.

14. The integrated circuit structure of claim 12 , wherein a liner comprising Titanium (Ti) and Nitrogen (N) surrounds nanowires of the second vertical arrangement of horizontal nanowires.

15. The integrated circuit structure of claim 12 , wherein the integrated circuit structure comprises transistors that operate in saturation mode on all nanowire sides regardless of a gate endcap tolerance between 3.5 nm and 10 nm even though an opposite polarity P-type conductive layer is over the second gate stack in the NMOS region.

16. The integrated circuit structure of claim 12 , wherein the N-type conductive layer comprising Titanium (Ti) and Nitrogen (N) has a thickness of approximately 3.5-4 nm, which is greater than a saturation thickness of 3-3.5 nm for the N-type conductive layer comprising Titanium (Ti) and Nitrogen (N).

17. The integrated circuit structure of claim 12 , wherein the P-type conductive layer has a thickness of approximately 3.5-4 nm, which is greater than a saturation thickness of 3.5 nm for the P-type conductive layer.

18. A computing device, comprising:
a board; and
a component coupled to the board, the component including an integrated circuit structure, comprising:
a first vertical arrangement of horizontal nanowires in a PMOS region;
a second vertical arrangement of horizontal nanowires in an NMOS region;
a first gate stack over the first vertical

Assignees

• Intel Corp

Inventors

• Lavric Dan S
• Crum Dax M
• Towner David J
• Acton Orb
• Jha Jitendra Kumar
• Chiu Yenting
• Haran Mohit K
• Golonzka Oleg
• Ghani Tahir

Classifications

• H10D84/85

  Complementary IGFETs, e.g. CMOS · CPC title

• H10D64/667

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN workfunction layers (having lateral variation H10D64/671) · CPC title

• H10D62/121

  oriented parallel to substrates · CPC title

• H10D30/6757

  characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile (TFTs having channel structures for preventing kink or snapback effects H10D30/6708; TFTs having lightly-doped source or drain extensions H10D30/6715) · CPC title

• H10D30/43

  having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels · CPC title