Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
US-10868535-B2 · Dec 15, 2020 · US
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Aarestad James patents
Aarestad James is listed as an inventor on 6 patents in our database. Major assignees and classification codes are summarized below.
| Metric | Value |
|---|---|
| Inventor | Aarestad James |
| Total patents | 6 |
| First publication | Jul 14, 2016 |
| Latest publication | Dec 15, 2020 |
Notable patents
Publications ranked by popularity score, then publication date.
Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
US-2020235735-A1 · Jul 23, 2020 · US
Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
US-10666256-B2 · May 26, 2020 · US
Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
US-2019089355-A1 · Mar 21, 2019 · US
Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
US-10230369-B2 · Mar 12, 2019 · US
Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
US-2016204781-A1 · Jul 14, 2016 · US
Recent patents
Latest publications not already listed above.
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Major assignees
Companies most often associated with this inventor's publications.
| Assignee | Patents |
|---|---|
| Stc Unm | 6 |
Top CPC classifications
Most common classification codes across this inventor's patents.
| CPC | Patents |
|---|---|
| H03K3/84 | 6 |
| H03K19/00323 | 6 |
| H03K19/215 | 6 |
| H04L9/0866 | 6 |
| H03K23/004 | 6 |