Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings

Patent metadata

Field	Value
Publication number	US-10666256-B2
Application number	US-201816185921-A
Country	US
Kind code	B2
Filing date	Nov 9, 2018
Priority date	Aug 28, 2013
Publication date	May 26, 2020
Grant date	May 26, 2020

Abstract

A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

First claim

The invention claimed is:

1. A method for generating a bitstring for a physically unclonable function, the method comprising the steps of:
measuring delay from logic paths, wherein the logic paths each have a different length;
recording a digitized representation of the measured path delays, wherein the digitized representation comprises physically unclonable function numbers (PNs);
determining one or more path delays from the recorded path delays;
applying a modulus operation to remove bias due to the different lengths, the modulus operation modifies the PNs of the one or more path delays; and
comparing one or more modified path delays.

2. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein the modulus operation partitions into two groups the path delay measurements.

3. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein the modulus operation reduces the PNs to a user-specified modulus value M or reduces the PNs within a range of values.

4. The method for generating a bitstring for a physically unclonable function according to claim 3 , wherein the user-specified modulus value M is a number between 8 and 30.

5. The method for generating a bitstring for a physically unclonable function according to claim 3 , wherein the range of values is 0 to M−1.

6. The method for generating a bitstring for a physically unclonable function according to claim 2 , wherein one of the two groups is a high PN group with modified path delay measurements having values in a range of M/2 to M−1 and M represents a user-specified modulus value.

7. The method for generating a bitstring for a physically unclonable function according to claim 2 , wherein one of the two groups is a low PN group with modified path delay measurements having values in a range of 0 to M/2−1 and M represents a user-specified modulus value.

8. The method for generating a bitstring for a physically unclonable function according to claim 1 , further comprising the step of:
applying a linear transformation to the recorded path delays correcting changes in temperature and voltage environmental conditions.

9. The method for generating a bitstring for a physically unclonable function according to claim 8 , wherein the linear transformation shifts and scales the measured path delays to match a reference distribution.

10. The method for generating a bitstring for a physically unclonable function according to claim 1 , further comprising the steps of:
computing a first mean PN during an enrollment phase;
computing a second mean PN during a regeneration phase;
calculating a difference value between the first mean PN and the second mean PN; and
adding the difference value to each PN obtained during the regeneration phase.

11. A device for generating a bitstring for a physically unclonable function comprising:
circuitry configured to measure delay from logic paths, wherein the logic paths each have a different length;
circuitry configured to record a digitized representation of the measured path delays, wherein the digitized representation comprises physically unclonable function numbers (PNs);
circuitry configured to determine one or more path delays from the recorded path delays;
circuitry configured to apply a modulus operation to remove bias due to the different lengths, the modulus operation modifies the PNs of the one or more path delays; and
circuitry configured to compare one or more modified path delays.

12. The device of claim 11 , wherein the modulus operation partitions into two groups the path delay measurements.

13. The device of claim 11 , wherein the modulus operation reduces the PNs to a user-specified modulus value M or reduces the PNs within a range of values.

14. The device of claim 13 , wherein the user-specified modulus value M is a number between 8 and 30.

15. The device of claim 13 , wherein the range of values is 0 to M−1.

16. The device of claim 12 , wherein one of the two groups is a high PN group with modified path delay measurements having values in a range of M/2 to M−1 and M represents a user-specified modulus value.

17. The device of claim 12 , wherein one of the two groups is a low PN group with modified path delay measurements having values in a range of 0 to M/2−1 and M represents a user-specified modulus value.

18. The device of claim 11 , further comprising circuitry configured to apply a linear transformation to the recorded path delays correcting changes in temperature and voltage environmental conditions.

19. The device of claim 18 , wherein the linear transformation shifts and scales the measured path delays to match a reference distribution.

20. The device of claim 11 , further comprising:
circuitry configured to compute a first mean PN during an enrollment phase;
circuitry configured to compute a second mean PN during a regeneration phase;
circuitry configured to compute a difference value between the first mean PN and the second mean PN; and
circuitry configured to compute add the difference value to each PN obtained during the regeneration phase.

21. The method for generating a bitstring for a physically unclonable function according to claim 9 , wherein the linear transformation subtracts a mean computed from a distribution of a regeneration phase and divides by a range also computed from the distribution of the regeneration phase.

22. The device of claim 19 , wherein the linear transformation subtracts a mean computed from a distribution of a regeneration phase and divides by a range also computed from the distribution of the regeneration phase.

Assignees

• Stc Unm

Inventors

• Plusquellic James
• Aarestad James

Classifications

• H03K3/84

  Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators · CPC title

• H03K19/00323 Primary

  Delay compensation · CPC title

• H03K19/215

  using field-effect transistors · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• H03K23/004

  Counters counting in a non-natural counting order, e.g. random counters · CPC title