Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings

Patent metadata

Field	Value
Publication number	US-10230369-B2
Application number	US-201414913454-A
Country	US
Kind code	B2
Filing date	Aug 28, 2014
Priority date	Aug 28, 2013
Publication date	Mar 12, 2019
Grant date	Mar 12, 2019

Abstract

A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

First claim

What is claimed is:

1. A method for generating a bitstring for a physically unclonable function, the method comprising:
measuring path delays corresponding to a set of launch-capture tests;
for each of the measured path delays, determining whether a respective path is a stable path, wherein the stable path is defined as a path which has a rising transition or a falling transition, is glitch-free, and produces consistent results across multiple launch-capture tests;
selecting one or more pairs of the stable paths of the measured path delays; and
generating a bitstring one bit at a time, wherein each bit is generated from each of the one or more pairs of the stable paths.

2. The method of claim 1 , wherein the pairs of the measured path delays are selected pseudorandomly.

3. The method of claim 1 , wherein a first measured path delay in a pair is less than a first threshold value and a second measured path delay in the pair is greater than a second threshold value.

4. The method of claim 1 , wherein generating a bitstring includes using a difference value of measured path delays to generate a bit, if it is determined that the difference value is greater than a threshold value.

5. The method of claim 1 , wherein generating a bitstring includes using a difference value of measured path delays to generate a bit, if it is determined that the difference value is greater than a lower threshold value and less than an upper threshold value.

6. The method of claim 1 , wherein generating a bitstring includes applying a modulus operation to digital representation of two or more of the measured path delays; and
partitioning the results of the modulus operation into two or more groups.

7. The method of claim 6 , wherein modulus operation is configured to remove bias.

8. The method of claim 1 , further comprising generating two or more redundant bitstrings and determining a final bitstring based on a majority rule.

9. A device for generating a bitstring for a physically unclonable function, the device comprising:
circuitry configured to measure path delays corresponding to a set of launch-capture tests;
circuitry configured to determine whether a path is stable, wherein a stable path is defined as a path which has a rising transition or a falling transition, is glitch-free, and produces consistent results across multiple launch-capture tests;
circuitry configured to select one or more pairs of stable paths; and
circuitry configured to generate a bitstring one bit at a time, wherein each bit is generated from each of the one or more pairs of the stable paths.

10. The device of claim 9 , wherein the pairs of the measured path delays are selected pseudorandomly.

11. The device of claim 9 , wherein a first measured path delay in a pair is less than a first threshold value and a second measured path delay in the pair is greater than a second threshold value.

12. The device of claim 9 , wherein generating a bitstring includes using a difference value of measured path delays to generate a bit, if it is determined that the difference value is greater than a threshold value.

13. The device of claim 9 , wherein generating a bitstring includes using a difference value of measured path delays to generate a bit, if it is determined that the difference value is greater than a lower threshold value and less than an upper threshold value.

14. The device of claim 9 , wherein generating a bitstring includes applying a modulus operation to digital representation of two or more of the measured path delays; and
partitioning the results of the modulus operation into two or more groups.

15. The device of claim 14 , wherein modulus operation is configured to remove bias.

16. The device of claim 9 , further comprising circuitry configured to generate two or more redundant bitstrings and determining a final bitstring based on a majority rule.

17. The method of claim 1 further comprising:
applying a linear transformation to the measured path delays correcting changes in temperature and voltage environmental conditions.

18. The method of claim 17 , wherein the linear transformation shifts and scales the measured path delays to match a reference distribution.

19. The device of claim 9 further comprising a linear transformation, wherein the linear transformation corrects changes in temperature and voltage environmental conditions of the measured path delays.

20. The device of claim 19 , wherein the linear transformation shifts and scales the measured path delays to match a reference distribution.

Assignees

• Stc Unm

Inventors

• Plusquellic James
• Aarestad James

Classifications

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• H04L9/0662

  with particular pseudorandom sequence generator · CPC title

• H03K19/00323 Primary

  Delay compensation · CPC title

• H03K23/004

  Counters counting in a non-natural counting order, e.g. random counters · CPC title