Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings

Patent metadata

Field	Value
Publication number	US-10868535-B2
Application number	US-202016843660-A
Country	US
Kind code	B2
Filing date	Apr 8, 2020
Priority date	Aug 28, 2013
Publication date	Dec 15, 2020
Grant date	Dec 15, 2020

Abstract

A Hardware-Embedded Delay PUF (HELP) leverages entropy by monitoring path stability and measuring path delays from core logic macros. HELP incorporates techniques to deal with bias. A unique feature of HELP is that it may compare data measured from different test structures. HELP may be implemented in existing FPGA platforms. HELP may leverage both path stability and within-die variations as sources of entropy.

First claim

The invention claimed is:

1. A method for generating a bitstring for a physically unclonable function, the method comprising the steps of:
selecting randomly a first digital representation of a first path delay (a first PN) and a second digital representation of a second path delay PN (a second PN);
producing an address of each of the selected first PN and the selected second PN;
providing to a first register the address of the selected first PN and providing to a second register the address of the selected second PN;
subtracting the second register from the first register to produce a PN difference value;
generating bits of the bitstring based on the subtracting step.

2. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein the first digital representation and the second digital representation consist of a range of values from 0 to 128.

3. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein a negative PN difference value produces a ‘0’ bit.

4. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein a positive PN difference value produces a ‘1’ bit.

5. The method for generating a bitstring for a physically unclonable function according to claim 1 further comprising the step of comparing the PN difference value to a threshold value.

6. The method for generating a bitstring for a physically unclonable function according to claim 5 , wherein the threshold value is based on a delay variation profile of a chip.

7. The method for generating a bitstring for a physically unclonable function according to claim 6 , wherein the threshold value is a noise threshold value calculated according to the steps:
subtracting a PN at the 5 th percentile of the delay variation profile and a PN at the 95 percentile of the delay variation profile to obtain a difference value; and
multiply the difference value by a noise margin to obtain the threshold value.

8. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein the first PN is longer in length than the second PN.

9. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein the bitstring generated is based on enrollment where a new bitstring is requested.

10. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein the bitstring generated is based on regeneration where a bitstring needs to be reproduced.

11. The method for generating a bitstring for a physically unclonable function according to claim 1 , wherein the providing step further comprises the step of reading the address of the selected first PN and the address of the selected second PN from an on-chip memory into the first register and the second register.

12. A device for generating a bitstring for a physically unclonable function comprising:
circuitry configured to select randomly a first digital representation of a first path delay (a first PN) and a second digital representation of a second path delay PN (a second PN);
circuitry configured to produce an address of each of the selected first PN and the selected second PN;
circuitry configured to provide to a first register the address of the selected first PN and provide to a second register the address of the selected second PN;
circuitry configured to subtract the second register from the first register to produce a PN difference value; and
circuitry configured to generate bits of the bitstring based on the PN difference value.

13. The device of claim 12 , wherein a negative PN difference value produces a ‘0’ bit and wherein a positive PN difference value produces a ‘1’ bit.

14. The device of claim 12 further comprising circuitry configured to compare the PN difference value to a threshold value.

15. The device of claim 14 , wherein the threshold value is based on a delay variation profile of a chip.

16. The device of claim 14 further comprising circuitry configured to subtract a PN at the 5 th percentile of the delay variation profile and a PN at the 95 percentile of the delay variation profile to obtain a difference value, and circuitry configured to multiply the difference value by a noise margin to obtain the threshold value.

17. The device of claim 12 , wherein the first PN is longer in length than the second PN.

18. The device of claim 12 , further comprising circuitry configured to read the address of the selected first PN and the address of the selected second PN from an on-chip memory into the first register and the second register.

Assignees

• Stc Unm

Inventors

• Plusquellic James
• Aarestad James

Classifications

• H03K19/00315

  in field-effect transistor circuits · CPC title

• H03K23/004

  Counters counting in a non-natural counting order, e.g. random counters · CPC title

• H04L9/0866

  involving user or device identifiers, e.g. serial number, physical or biometrical information, DNA, hand-signature or measurable physical characteristics · CPC title

• H03K19/00323 Primary

  Delay compensation · CPC title

• H04L9/0662

  with particular pseudorandom sequence generator · CPC title