Semiconductor device and methods of making and using an enhanced carrier to reduce electrostatic discharge
US-12588463-B2 · Mar 24, 2026 · US
characterised by a material, a roughness, a coating or the like
characterised by a material, a roughness, a coating or the like · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H10P72/145 |
| Official title | {characterised by a material, a roughness, a coating or the like} |
| Display label | characterised by a material, a roughness, a coating or the like |
| Total patents | 33 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly growing.
| Year | Patents |
|---|---|
| 2015 | 1 |
| 2016 | 2 |
| 2018 | 3 |
| 2019 | 2 |
| 2020 | 2 |
| 2021 | 2 |
| 2022 | 3 |
| 2023 | 7 |
| 2024 | 4 |
| 2025 | 5 |
| 2026 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Substrate storage racks for semiconductor processing systems
US-2026018443-A1 · Jan 15, 2026 · US
Method and apparatus for forming semiconductor device
US-2025364275-A1 · Nov 27, 2025 · US
Substrate Transfer Module and Method for Manufacturing Substrate Transfer Module
US-2025232994-A1 · Jul 17, 2025 · US
Semiconductor substrate boat and methods of using the same
US-12308266-B2 · May 20, 2025 · US
Semiconductor processing apparatus and method utilizing electrostatic discharge (ESD) prevention layer
US-12255091-B2 · Mar 18, 2025 · US
Processing chamber with annealing mini-environment
US-12249522-B2 · Mar 11, 2025 · US
Semiconductor substrate boat and methods of using the same
US-2024379394-A1 · Nov 14, 2024 · US
Semiconductor Device and Methods of Making and Using an Enhanced Carrier to Reduce Electrostatic Discharge
US-2024355655-A1 · Oct 24, 2024 · US
Advanced method for creating electrostatic chuck (esc) mesa patterns
US-2024339349-A1 · Oct 10, 2024 · US
Semiconductor processing apparatus and method utilizing electrostatic discharge (esd) prevention layer
US-2024087945-A1 · Mar 14, 2024 · US
Processing chamber with annealing mini-environment
US-2023420275-A1 · Dec 28, 2023 · US
Semiconductor processing apparatus and method utilizing electrostatic discharge (ESD) prevention layer
US-11854860-B2 · Dec 26, 2023 · US
Processing chamber with annealing mini-environment
US-11791176-B2 · Oct 17, 2023 · US
Methods and systems having conductive polymer coating for electrostatic discharge applications
US-2023197491-A1 · Jun 22, 2023 · US
Substrate storage racks for semiconductor processing systems
US-2023143667-A1 · May 11, 2023 · US
Semiconductor processing apparatus and method utilizing electrostatic discharge (esd) prevention layer
US-2023077331-A1 · Mar 16, 2023 · US
Workpiece support system for plasma treatment and method of using the same
US-2023018842-A1 · Jan 19, 2023 · US
Manufacturing method of ESD protection device
US-11328946-B2 · May 10, 2022 · US
Semiconductor substrate boat and methods of using the same
US-2022102175-A1 · Mar 31, 2022 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H10P72/145?
- CPC H10P72/145 is the Cooperative Patent Classification code for “characterised by a material, a roughness, a coating or the like.”
- How many patents are filed under CPC H10P72/145 (characterised by a material, a roughness, a coating or the like)?
- Our database includes 33 publications tagged with this CPC code.
- Is patent activity under CPC H10P72/145 growing?
- Publication counts under this code: 4 in 2024 vs 5 in 2025 (latest complete years).