Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)
US-12450191-B2 · Oct 21, 2025 · US
the pulses having two levels
the pulses having two levels · Cooperative Patent Classification (CPC)
Electric circuits, power, telecommunications, and semiconductors.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | H03M5/04 |
| Official title | the pulses having two levels |
| Display label | the pulses having two levels |
| Total patents | 52 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 7 |
| 2016 | 6 |
| 2017 | 5 |
| 2018 | 5 |
| 2019 | 6 |
| 2020 | 5 |
| 2021 | 5 |
| 2022 | 5 |
| 2023 | 4 |
| 2024 | 2 |
| 2025 | 2 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Methods and systems for high bandwidth communications interface
US-12206531-B2 · Jan 21, 2025 · US
Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (fpga)
US-2024152484-A1 · May 9, 2024 · US
Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)
US-11874792-B2 · Jan 16, 2024 · US
Two-level coding/decoding-based touch sensing device and touch sensing method for mutual capacitance touch sensor
US-11662857-B2 · May 30, 2023 · US
Energy efficient adaptive data encoding method and circuit
US-11658681-B2 · May 23, 2023 · US
Direct mapping
US-11621012-B2 · Apr 4, 2023 · US
Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (fpga)
US-2023038814-A1 · Feb 9, 2023 · US
Methods and apparatus for providing a serializer and deserializer (SERDES) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)
US-11474969-B1 · Oct 18, 2022 · US
Methods and systems for high bandwidth communications interface
US-2022329467-A1 · Oct 13, 2022 · US
Methods and systems for high bandwidth communications interface
US-11374801-B2 · Jun 28, 2022 · US
Efficient encoding methods using bit inversion and padding bits
US-11368166-B2 · Jun 21, 2022 · US
Two-Level Coding/Decoding-Based Touch Sensing Device and Touch Sensing Method for Mutual Capacitance Touch Sensor
US-2022187944-A1 · Jun 16, 2022 · US
Direct mapping
US-2021358509-A1 · Nov 18, 2021 · US
Efficient Encoding Methods
US-2021351786-A1 · Nov 11, 2021 · US
Energy efficient adaptive data encoding method and circuit
US-2021320672-A1 · Oct 14, 2021 · US
Converting a single-bit audio stream to a stream of symbols with a constant edge rate
US-11107485-B2 · Aug 31, 2021 · US
Energy efficient adaptive data encoding method and circuit
US-11038526-B2 · Jun 15, 2021 · US
Parallel-to-serial conversion circuit
US-10797725-B2 · Oct 6, 2020 · US
Parallel-to-serial conversion circuit
US-2020195274-A1 · Jun 18, 2020 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC H03M5/04?
- CPC H03M5/04 is the Cooperative Patent Classification code for “the pulses having two levels.”
- How many patents are filed under CPC H03M5/04 (the pulses having two levels)?
- Our database includes 52 publications tagged with this CPC code.
- Is patent activity under CPC H03M5/04 growing?
- Publication counts under this code: 2 in 2024 vs 2 in 2025 (latest complete years).