Energy efficient adaptive data encoding method and circuit

Patent metadata

Field	Value
Publication number	US-11038526-B2
Application number	US-202016792486-A
Country	US
Kind code	B2
Filing date	Feb 17, 2020
Priority date	Aug 22, 2017
Publication date	Jun 15, 2021
Grant date	Jun 15, 2021

Abstract

Various energy efficient data encoding schemes and computing devices are disclosed. In one aspect, a method of transmitting data from a transmitter to a receiver connected by plural wires is provided. The method includes sending from the transmitter on at least one but not all of the wires a first wave form that has first and second signal transitions. The receiver receives the first waveform and measures a first duration between the first and second signal transitions using a locally generated clock signal not received from the transmitter. The first duration is indicative of a first particular data value.

First claim

What is claimed is:

1. A semiconductor chip, comprising:
a receiver having a circuit to generate a local clock signal;
a transmitter connected to the receiver by plural wires; and
wherein the semiconductor chip is configured to selectively operate in an efficiency-based encoding mode and while operating in efficiency-based encoding mode sending from the transmitter to the receiver on at least one but not all of the wires a first wave form having first and second consecutive signal transitions, and wherein the receiver is configured to receive the first wave form and measure a first duration between the first and second consecutive signal transitions using the local clock signal, wherein the first duration represents a first particular multi-bit data value.

2. The semiconductor chip of claim 1 , wherein the semiconductor chip comprises a microprocessor, a graphics processing unit, an accelerated processing unit.

3. The semiconductor chip of claim 1 , wherein the local clock signal includes a series of high and low states, the receiver being configured to delay commencement of measurement of the first duration while the local clock signal is in a low state.

4. The semiconductor chip of claim 1 , wherein the receiver includes an edge detector and a counter, the edge detector being configured to detect the first signal transition and in response thereto generate a pulse, and the counter being configured to receive the pulse and commence counting clock cycles upon receipt of the pulse, and the edge detector being configured to detect the second signal transition and in response thereto generate another pulse, the counter being configured to receive the another pulse and cease counting clock cycles upon receipt of the another pulse.

5. The semiconductor chip of claim 4 , wherein the counter is configured to generate a received value based on the counted clock cycles.

6. The semiconductor chip of claim 1 , wherein the receiver includes a mapping of a known data value to the first duration between the first and second consecutive signal transitions.

7. The semiconductor chip of claim 1 , wherein the transmitter is configured to send to the receiver on at least one other of the wires a second wave form having first and second consecutive signal transitions, and the receiver is configured to receive the second wave form and measure a second duration between the first and second consecutive signal transitions using the local clock signal, the second duration being indicative of a second particular data value.

8. The semiconductor chip of claim 7 , wherein the receiver is configured to combine the first particular multi-bit data value and the second particular data value into a combined data value.

9. A semiconductor chip, comprising:
a receiver including plural serial receiver circuits, each of the serial receiver circuits having a circuit to generate a local clock signal, and a transmitter connected to the serial receiver circuits by plural wires, the semiconductor chip being configured to selectively operate in an efficiency-based encoding mode and while operating in efficiency-based encoding mode sending from the transmitter to the receiver on at least one but not all of the wires a first wave form having first and second consecutive signal transitions; and
wherein the receiver is configured to receive the first wave form and measure a first duration between the first and second consecutive signal transitions using at least one of the local clock signals, wherein the first duration represents a first particular multi-bit data value.

10. The semiconductor chip of claim 9 , where each of the serial receiver circuits comprises a counter to count clock cycles of the local clock signal and generate a received value based on the counted clock cycles, and a training controller connected to the counter and operable in a training mode and an operational mode, the training controller being operable, while in the training mode, to receive a sequence of numbers and a sequence of wave forms wherein each of the wave forms has a duration between rising and falling edges corresponding to one of the numbers, and to store the numbers and the corresponding durations in a look up table for use by the counter during the operational mode.

11. The semiconductor chip of claim 9 , wherein the circuit to generate the local clock signal comprises a C-element having an output connected to the counter, a first input connected to the output, and a second input, the C-element being operable to output a first logic level if the first input and the second input are both at the first logic level or to output a second logic level if the first input and the second input are not both at the first logic level in order to bring the first input and the second input both to the first logic level.

12. The semiconductor chip of claim 11 , wherein the first input comprises an inverter and a programmable delay line.

13. The semiconductor chip of claim 9 , wherein the local clock signal includes a series of high and low states, each of the serial receiver circuits being configured to delay commencement of measurement of the first duration while the local clock signal is in a low state.

14. The semiconductor chip of claim 9 , wherein each of the serial receiver circuits comprises an edge detector and a counter to count clock cycles of the local clock signal and generate a received value based on the counted clock cycles, the edge detector being configured to detect the first signal transition and in response thereto generate a pulse, and the counter being configured to receive the pulse and commence counting clock cycles upon receipt of the pulse, and the edge detector being configured to detect the second signal transition and in response thereto generate another pulse, the counter being configured to receive the another pulse and cease counting clock cycles upon receipt of the another pulse.

15. The semiconductor chip of claim 9 , wherein each of the serial receiver circuits includes a mapping of a known data value to the duration between the first and second consecutive signal transitions.

16. The semiconductor chip of claim 9 , wherein the transmitter is configured to send to one of the serial receiver circuits on at least one other of the wires a second wave form having first and second consecutive signal transitions, and the serial receiver circuit is configured to receive the second wave form and measure a second duration between the first and second consecutive signal transitions using the local clock signal, the second duration being indicative of a second particular data value.

17. The semiconductor chip of claim 16 , wherein the receiver is configured to combine the first particular multi-bit data value and the second particular data value into a combined data value.

18. A computing device, comprising:
a receiver having a circuit to generate a local clock signal;
a transmitter connected to the receiver by plural wires;
the computing device being configured to selectively operate in an efficiency-based encoding mode and while operating in efficiency-based encoding mode sending from the transmitter to the receiver on at least one but not all of the wires a first wave form having first and second consecutive signal transitions; and
wherein the receiver is configured to receive the first wave form and measure a first duration between the first and second consecutive signal transitions using the local clock signal, wherein the first duration represents a first particular multi-bit data value.

1

Assignees

• Advanced Micro Devices Inc

Inventors

• Sadowski Greg
• Kalamatianos John

Classifications

• H04B3/54 Primary

  Systems for transmission via power distribution lines · CPC title

• H03M7/6047 Primary

  Power optimization with respect to the encoder, decoder, storage or transmission · CPC title

• H04B1/04

  Circuits · CPC title

• H04B1/16

  Circuits · CPC title

• H03M5/04

  the pulses having two levels · CPC title