Parallel-to-serial conversion circuit

Patent metadata

Field	Value
Publication number	US-10797725-B2
Application number	US-201916713414-A
Country	US
Kind code	B2
Filing date	Dec 13, 2019
Priority date	Dec 17, 2018
Publication date	Oct 6, 2020
Grant date	Oct 6, 2020

Abstract

A parallel-to-serial conversion circuit may include first to fourth data lines; first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line, wherein two of the first to fourth drivers are simultaneously activated.

First claim

What is claimed is:

1. A parallel-to-serial conversion circuit comprising:
first to fourth data lines;
first to fourth parallel-to-serial converters configured to parallel-to-serial convert data of corresponding two data lines, among the first to fourth data lines, at a ratio of 2:1, respectively; and
first to fourth drivers configured to transmit converted data of corresponding parallel-to-serial converter, among the first to fourth parallel-to-serial converters, respectively, to an output line,
wherein two of the first to fourth drivers are simultaneously activated.

2. The parallel-to-serial conversion circuit of claim 1 , wherein the first parallel-to-serial converter parallel-to-serial converts data of the fourth data line and data of the first data line at a ratio of 2:1,
the second parallel-to-serial converter parallel-to-serial converts the data of the first data line and data of the second data line at a ratio of 2:1,
the third parallel-to-serial converter parallel-to-serial converts the data of the second data line and data of the third data line at a ratio of 2:1, and
the fourth parallel-to-serial converter parallel-to-serial converts the data of the third data line and data of the fourth data line at a ratio of 2:1.

3. The parallel-to-serial conversion circuit of claim 2 , wherein the fourth driver and the first driver are activated during a first period,
the first driver and the second driver are activated during a second period,
the second driver and the third driver are activated during a third period, and
the third driver and the fourth driver are activated during a fourth period.

4. The parallel-to-serial conversion circuit of claim 3 , wherein each of the first to fourth parallel-to-serial converters and each of the first to fourth drivers operate in synchronization with at least one of first to fourth docks with phases different from one another.

5. A parallel-to-serial conversion circuit comprising:
first to fourth data lines;
a first parallel-to-serial converter configured to parallel-to-serial convert data of the fourth data line and data of the first data line at a ratio of 2:1;
a second parallel-to-serial converter configured to parallel-to-serial convert the data of the first data line and data of the second data line at a ratio of 2:1;
a third parallel-to-serial converter configured to parallel-to-serial convert the data of the second data line and data of the third data line at a ratio of 2:1;
a fourth parallel-to-serial converter configured to parallel-to-serial convert the data of the third data line and data of the fourth data line at a ratio of 2:1;
a first driver configured to be activated in response to a first clock and to transmit converted data of the first parallel-to-serial converter to an output line;
a second driver configured to be activated in response to a second clock with a phase difference of 90° with respect to the first clock and to transmit converted data of the second parallel-to-serial converter to the output line;
a third driver configured to be activated in response to a third clock with a phase difference of 90° with respect to the second clock and to transmit converted data of the third parallel-to-serial converter to the output line; and
a fourth driver configured to be activated in response to a fourth clock with a phase difference of 90° with respect to the third clock and to transmit converted data of the fourth parallel-to-serial converter to the output line.

6. The parallel-to-serial conversion circuit of claim 5 , wherein the first parallel-to-serial converter selects and outputs the data of the fourth data line when the fourth clock is activated, and selects and outputs the data of the first data line when the fourth clock is deactivated,
the second parallel-to-serial converter selects and outputs the data of the first data line when the first clock is activated, and selects and outputs the data of the second data line when the first clock is deactivated,
the third parallel-to-serial converter selects and outputs the data of the second data line when the second clock is activated, and selects and outputs the data of the third data line when the second clock is deactivated, and
the fourth parallel-to-serial converter selects and outputs the data of the third data line when the third clock is activated, and selects and outputs the data of the fourth data line when the third clock is deactivated.

7. A circuit comprising:
a plurality of data lines in parallel, configured to output a plurality of input data; and
a plurality of data converters configured to receive the plurality of input data in parallel and convert the plurality of input data to a plurality of output data in series, each input data having a first rate, each output data having a second rate corresponding to a quarter of the first rate,
wherein each of the plurality of data converters:
receives a pair including two different input data among the plurality of input data;
generates the two input data as two serial data, each of the two serial data having a third rate corresponding to half of the first rate; and
outputs the two serial data as two output data among the plurality of output data.

8. The circuit of claim 7 , wherein the plurality of data converters comprises:
a plurality of parallel-to-serial converters; and
a plurality of drivers,
wherein each of plurality of parallel-to-serial converters receives a corresponding pair among the plurality of input data, and generates corresponding two serial data,
wherein each of the plurality of drivers receives corresponding two serial data and corresponding two output data among the plurality of output data.

Assignees

• Sk Hynix Inc
• Seoul Nat Univ R&Db Foundation

Inventors

• Kim Suhwan
• Chae Joo-Hyung

Classifications

• H03M9/00 Primary

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H03M5/04

  the pulses having two levels · CPC title

• H03M7/04

  the radix thereof being two · CPC title