Methods and apparatus for providing a serializer and deserializer (serdes) block facilitating high-speed data transmissions for a field-programmable gate array (FPGA)

Patent metadata

Field	Value
Publication number	US-12450191-B2
Application number	US-202418414403-A
Country	US
Kind code	B2
Filing date	Jan 16, 2024
Priority date	May 12, 2021
Publication date	Oct 21, 2025
Grant date	Oct 21, 2025

Abstract

A method for providing a high-speed data communication between a host and field-programmable gate array (“FPGA”) is disclosed. The method, in one embodiment, is capable of identifying a data rate on a bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol. Upon sampling, by a first input deserializer, first two samples of data signals carried by the P-channel in accordance with a first clock signals clocking twice as fast as the data rate of the P-channel, a second input deserializer is used to sample the second two samples of data signals transmitted by the N-channel in accordance with a second clock signal running twice as fast as the data rate of the N-channel with a ninety (90) degree phase shift. The method subsequently forwards the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

First claim

What is claimed is:

1. An apparatus for network communication containing a programmable device able to perform user configurable logic functions, comprising:
a field-programmable gate array (“FPGA”) containing a first input deserializer configured to obtain a first sample on P-channel of a Universal Serial Bus (“USB”) bus in accordance with a first clock frequency, and a second input deserializer configured to obtain second samples on N-channel of USB bus in accordance with a second clock frequency; and
a sample decoder coupled to the first input deserializer and configured to generate decoded data in response to the first and second samples.

2. The apparatus of claim 1 , wherein the first input deserializer is configured to receive first of two samples of data signals on the P-channel in accordance with a first clock having a clock cycle running twice speed as data rate at the P-channel.

3. The apparatus of claim 1 , wherein the second input deserializer is configured to obtain the second of two samples of data signals on the N-channel in accordance with a second clock with a ninety (90) degree phase shift of a first clock wherein the second clock having a clock cycle running twice speed as data rate at the N-channel.

4. The apparatus of claim 1 , further comprising a host computer capable of facilitating high-speed (“HS”) network data transmission.

5. The apparatus of claim 1 , further a bus coupled to a host computer for providing HS serial data transmission.

6. The apparatus of claim 1 , wherein the FPGA includes a drive block configured to establish a handshaking process between a host computer and the FPGA via a bus for HS data transmissions.

7. The apparatus of claim 1 , wherein the FPGA includes an IO serdes block (“ISB”) configured to facilitate serdes operation at high-speed data rate without employing clock synchronizing circuitry.

8. The apparatus of claim 1 , wherein the USB bus includes a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol.

9. The apparatus of claim 1 , wherein the FPGA includes a plurality of configurable logic blocks (“LBs”) coupled to the first input deserializer and configured to be selectively programmed to perform one or more user defined logic functions.

10. The apparatus of claim 1 , wherein the sample decoder is able to adjust clocking times for the first clock and the second clock to compensate bit slips due to clock drift.

11. The apparatus of claim 7 , wherein the ISB includes a non-return-to-zero-inverted (“NRZI”) decoder coupled to the sample decoder and configured to remove bit stuff from the decoded data.

12. The apparatus of claim 7 , wherein the ISB includes a first clock clocking at 960 mega bit per second (“Mbps”).

13. The apparatus of claim 12 , wherein the ISB includes a second clock is clocking at 960 Mbps with a ninety (90) degree phase shift.

14. The apparatus of claim 12 , wherein the ISB includes a transmitter coupled to an 8:1 output serializer and configured to transmit the stream of serial bits in accordance with a clock speed of 480 megabits per second.

15. A method of providing a high-speed (“HS”) signal transmission between a host and field-programmable gate array (“FPGA”), comprising:
connecting an FPGA to a host via a bus capable of supporting HS network data transmission;
activating a first input deserializer of FPGA to receive a first sample of multiple samples on P-channel of a Universal Serial Bus (“USB”) bus in accordance with a first clock frequency;
activating a second input deserializer of FPGA to obtain a second sample of the multiple samples on N-channel of USB bus in accordance with a second clock frequency; and
coupling a sample decoder to the first input deserializer for generating decoded data in response to the first and second samples.

16. The method of claim 15 , further comprising activating a drive block of FPGA to negotiate transmission speed for identifying a data rate on the bus containing a P-channel and an N-channel operable to transmit signals in accordance with a high-speed Universal Serial Bus (“USB”) protocol.

17. The method of claim 15 , further comprising forwarding the data signals to one or more configurable logic blocks (“LBs”) in FPGA.

18. The method of claim 15 , further comprising decoding, by the sample decoder, the data signals sampled by the first and the second input deserializers to generate decoded data based on the first two samples of data signals and the second two samples of data signals.

19. The method of claim 15 , further comprising adjusting, by the sample decoder, clocking times for the first clock signal to compensate bit slips due to clock drift based on information obtained from the first two samples and the second two samples.

20. An apparatus of providing a high-speed (“HS”) signal transmission between a host and field-programmable gate array (“FPGA”), comprising:
means for connecting an FPGA to a host via a bus capable of supporting HS network data transmission;
means for activating a first input deserializer of FPGA to receive a first sample of multiple samples on P-channel of a Universal Serial Bus (“USB”) bus in accordance with a first clock frequency;
means for activating a second input deserializer of FPGA to obtain a second sample of the multiple samples on N-channel of USB bus in accordance with a second clock frequency; and
means for coupling a sample decoder to the first input deserializer for generating decoded data in response to the first and second samples.

Assignees

• Gowin Semiconductor Corp

Inventors

• Jennings Grant Thomas

Classifications

• H03M5/04

  the pulses having two levels · CPC title

• H03M9/00

  Parallel/series conversion or vice versa (digital stores in which the information is moved stepwise per se G11C19/00) · CPC title

• H03K19/17744

  for input/output signals · CPC title

• G06F2213/0042

  Universal serial bus [USB] · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title