Transistor, clocked inverter circuit, sequential circuit, and semiconductor device including sequential circuit

Patent metadata

Field	Value
Publication number	US-9887299-B2
Application number	US-201615279513-A
Country	US
Kind code	B2
Filing date	Sep 29, 2016
Priority date	Sep 13, 2013
Publication date	Feb 6, 2018
Grant date	Feb 6, 2018

Abstract

A transistor with excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics) is provided. The transistor includes an oxide semiconductor layer including a channel formation region, a first gate electrode, a second gate electrode, a source electrode, and a drain electrode. The oxide semiconductor layer is between the first gate electrode and the second gate electrode. The oxide semiconductor layer has a pair of side surfaces in contact with the source electrode and the drain electrode and includes a region surrounded by the first gate electrode and the second gate electrode without the source electrode and the drain electrode interposed therebetween.

First claim

What is claimed is:

1. A semiconductor device comprising:
a first gate electrode over a substrate;
a first insulating layer over the first gate electrode;
a first metal oxide layer including a channel formation region over the first insulating layer;
a second metal oxide layer over the first metal oxide layer;
a source electrode in contact with a first side surface of the first metal oxide layer;
a drain electrode in contact with a second side surface of the first metal oxide layer;
a second insulating layer over the second metal oxide layer, the source electrode, and the drain electrode; and
a second gate electrode over the second insulating layer,
wherein the first gate electrode overlaps with the first metal oxide layer,
wherein the second gate electrode is in contact with the first gate electrode in at least one opening in the first insulating layer and the second insulating layer, and
wherein a third surface of the first metal oxide layer faces the second gate electrode with the second insulating layer interposed therebetween and without the source electrode and the drain electrode interposed therebetween.

2. The semiconductor device according to claim 1 , wherein a thickness of the first metal oxide layer is larger than a thickness of the second metal oxide layer.

3. The semiconductor device according to claim 1 ,
wherein the first metal oxide layer comprises indium, gallium, and zinc, and
wherein the second metal oxide layer comprises indium, gallium, and zinc.

4. The semiconductor device according to claim 3 , wherein the second metal oxide layer comprises more gallium than the first metal oxide layer.

5. The semiconductor device according to claim 1 ,
wherein the first metal oxide layer comprises indium, gallium, and zinc, and
wherein the second metal oxide layer comprises indium and gallium.

6. The semiconductor device according to claim 5 , wherein the second metal oxide layer comprises more gallium than indium.

7. The semiconductor device according to claim 1 , wherein each of the source electrode and the drain electrode comprises copper.

8. The semiconductor device according to claim 1 ,
wherein the source electrode is in contact with the first side surface of the second metal oxide layer, and
wherein the drain electrode is in contact with the second side surface of the second metal oxide layer.

9. A semiconductor device comprising:
a first gate electrode over a substrate;
a first insulating layer over the first gate electrode;
a first metal oxide layer including a channel formation region over the first insulating layer;
a second metal oxide layer over the first metal oxide layer;
a source electrode and a drain electrode, each of the source electrode and the drain electrode comprising a first conductive layer and a second conductive layer over the first conductive layer,
a second insulating layer over the second metal oxide layer, the source electrode, and the drain electrode; and
a second gate electrode over the second insulating layer,
wherein the first gate electrode overlaps with the first metal oxide layer,
wherein the second gate electrode is in contact with the first gate electrode in at least one opening in the first insulating layer and the second insulating layer,
wherein the first conductive layer of the source electrode is in contact with a first side surface of the first metal oxide layer;
wherein the first conductive layer of the drain electrode is in contact with a second side surface of the first metal oxide layer; and
wherein a third surface of the first metal oxide layer faces the second gate electrode with the second insulating layer interposed therebetween and without the source electrode and the drain electrode interposed therebetween.

10. The semiconductor device according to claim 9 , wherein a thickness of the first metal oxide layer is larger than a thickness of the second metal oxide layer.

11. The semiconductor device according to claim 9 ,
wherein the first metal oxide layer comprises indium, gallium, and zinc, and
wherein the second metal oxide layer comprises indium, gallium, and zinc.

12. The semiconductor device according to claim 11 , wherein the second metal oxide layer comprises more gallium than the first metal oxide layer.

13. The semiconductor device according to claim 9 ,
wherein the first metal oxide layer comprises indium, gallium, and zinc, and
wherein the second metal oxide layer comprises indium and gallium.

14. The semiconductor device according to claim 13 , wherein the second metal oxide layer comprises more gallium than indium.

15. The semiconductor device according to claim 9 , wherein the second conductive layer comprises copper.

16. The semiconductor device according to claim 9 ,
wherein the first conductive layer of the source electrode is in contact with the first side surface of the second metal oxide layer, and
wherein the first conductive layer of the drain electrode is in contact with the second side surface of the second metal oxide layer.

17. The semiconductor device according to claim 9 , wherein a thickness of the second conductive layer is larger than a thickness of the first conductive layer.

Assignees

• Semiconductor Energy Lab

Inventors

• Yamazaki Shunpei
• Katayama Masahiro
• Okazaki Kenichi
• Koyama Jun

Classifications

• H03K19/096

  Synchronous circuits, i.e. using clock signals {(H03K19/01728, H03K19/01855 take precedence)} · CPC title

• H03K19/09443

  using a combination of enhancement and depletion transistors · CPC title

• H03K3/356121

  with synchronous operation (H03K3/35613, H03K3/356147 take precedence) · CPC title

• H03K3/037

  Bistable circuits · CPC title

• H03K5/15093

  using devices arranged in a shift register · CPC title