Full adder cell with improved power efficiency

Patent metadata

Field	Value
Publication number	US-11169779-B2
Application number	US-202016803795-A
Country	US
Kind code	B2
Filing date	Feb 27, 2020
Priority date	Oct 23, 2019
Publication date	Nov 9, 2021
Grant date	Nov 9, 2021

Abstract

An adder circuit provides a first operand input and a second operand input to an XNOR cell. The XNOR cell transforms these inputs to a propagate signal that is applied to an OAT cell to produce a carry out signal. A third OAT cell transforms a third operand input and the propagate signal into a sum output signal.

First claim

What is claimed is:

1. An adder circuit comprising:
a first operand input and a second operand input to an XNOR cell;
an OAI cell transforming an output of the XNOR cell into a carry out signal; and
an XOR cell comprising a NOR gate and an AOI cell configured to transform a third operand input and the output of the XNOR cell into a sum output signal.

2. The adder circuit of claim 1 , wherein the XNOR cell comprises a NAND gate coupled to an input of the OAI cell.

3. The adder circuit of claim 1 , wherein an output of the NOR gate is coupled to an input of the AOI cell.

4. The adder circuit of claim 1 , wherein an output of the NOR gate is coupled to an input of the OAI cell.

5. The adder circuit of claim 1 , wherein the third operand input is a complement operand input.

6. The adder circuit of claim 1 , wherein the third operand input is an un-complemented operand input.

7. The adder circuit of claim 1 , wherein the sum output signal is an un-complemented sum output signal.

8. The adder circuit of claim 1 , wherein the sum output signal is a complement sum output signal.

9. A compressor circuit comprising:
a first full adder;
a second full adder; and
each full adder comprising:
a first operand input and a second operand input to both of a NAND gate and a first OAI cell;
a second OAI cell to transform outputs of the NAND gate and the first OAI cell into a carry out signal; and
an output stage comprising an AOI cell to transform outputs of the first OAI cell and a third operand input into a sum output signal.

10. The compressor circuit of claim 9 , wherein a sum output of the first full adder is applied to an input stage of the second full adder without an intervening inverter.

11. The compressor circuit of claim 10 , wherein the sum output is a complement sum output.

12. The compressor circuit of claim 9 , further comprising:
a third full adder coupled to a sum output of the second full adder.

13. An adder circuit comprising:
an XNOR cell;
an OAI cell;
an AOI cell; and
the XNOR cell configured to transform a first operand input and a second operand input into a propagate signal applied to each of the OAI cell and the AOI cell.

14. The adder circuit of claim 13 , the XNOR cell further configured to output a generate signal.

15. The adder circuit of claim 14 , the OAI cell configured to transform the propagate signal and the generate signal into a carry out signal.

16. The adder circuit of claim 14 , the OAI cell further configured to receive a third input.

17. The adder circuit of claim 16 , wherein the third input is a third operand input of the adder circuit.

18. The adder circuit of claim 16 , wherein the third input is the propagate signal NORed with a third operand input of the adder circuit.

19. A compressor circuit comprising:
a first full adder;
a second full adder; and
the second full adder comprising:
a first operand input and a carry in input to both of a NAND gate and a first OAI cell;
a second OAI cell transforming outputs of the NAND gate and the first OAI cell into a carry out signal; and
an AOI cell transforming outputs of the first OAI cell and a complement sum input signal into a sum output signal.

Assignees

• Nvidia Corp

Inventors

• Elkin Ilyas
• Yang Ge
• Zhang Xi

Classifications

• G06F7/501 Primary

  Half or full adders, i.e. basic adder cells for one denomination · CPC title

• H03K19/215

  using field-effect transistors · CPC title

• G06F9/30029

  Logical and Boolean instructions, e.g. XOR, NOT · CPC title

• G06F9/3001

  Arithmetic instructions · CPC title

• G06F7/575

  Basic arithmetic logic units, i.e. devices selectable to perform either addition, subtraction or one of several logical operations, using, at least partially, the same circuitry · CPC title