Efficient resolution of latch race conditions in emulation
US-10140413-B2 · Nov 27, 2018 · US
Testing of logic operation, e.g. by logic analysers
Testing of logic operation, e.g. by logic analysers · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F11/25 |
| Official title | Testing of logic operation, e.g. by logic analysers |
| Display label | Testing of logic operation, e.g. by logic analysers |
| Total patents | 146 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is rapidly declining.
| Year | Patents |
|---|---|
| 2015 | 17 |
| 2016 | 18 |
| 2017 | 15 |
| 2018 | 18 |
| 2019 | 29 |
| 2020 | 9 |
| 2021 | 9 |
| 2022 | 8 |
| 2023 | 9 |
| 2024 | 8 |
| 2025 | 3 |
| 2026 | 3 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Jtag lockout for embedded processors in programmable devices
US-2018292458-A1 · Oct 11, 2018 · US
Test circuit to debug missed test clock pulses
US-2018284192-A1 · Oct 4, 2018 · US
Single circuit fault detection
US-2018284188-A1 · Oct 4, 2018 · US
Apparatus and methods for logic analysis to detect trigger conditions relating to data handling transactions in systems using transaction identifiers
US-10061671-B2 · Aug 28, 2018 · US
System and simulator for the disengageable simulation of installations or machines within programmable logic controllers
US-2018203973-A1 · Jul 19, 2018 · US
Memory circuit and method of operating a memory circuit
US-2018158534-A1 · Jun 7, 2018 · US
Automatic generation of an exception detector for determining an overflow condition
US-2018137030-A1 · May 17, 2018 · US
Clock selection circuit and test clock generation circuit for lbist and atpg test circuit
US-2018080987-A1 · Mar 22, 2018 · US
Persistent command parameter table for pre-silicon device testing
US-2018018250-A1 · Jan 18, 2018 · US
Test apparatus, memory test system, and test method
US-2017372792-A1 · Dec 28, 2017 · US
Apparatuses and methods for a multiple master capable debug interface
US-2017356961-A1 · Dec 14, 2017 · US
Commit sensitive tests
US-9842044-B2 · Dec 12, 2017 · US
Condition monitoring device and condition monitoring method for extracted-gas compression system, and extracted-gas compression system
US-2017284386-A1 · Oct 5, 2017 · US
Semiconductor device
US-2017285106-A1 · Oct 5, 2017 · US
Delayed authentication debug policy
US-9759768-B2 · Sep 12, 2017 · US
Memory circuit defect correction
US-2017186500-A1 · Jun 29, 2017 · US
Test apparatus and testable asynchronous circuit
US-2017160340-A1 · Jun 8, 2017 · US
Scan compression architecture for highly compressed designs and associated methods
US-2017140838-A1 · May 18, 2017 · US
Persistent command parameter table for pre-silicon device testing
US-9619312-B2 · Apr 11, 2017 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F11/25?
- CPC G06F11/25 is the Cooperative Patent Classification code for “Testing of logic operation, e.g. by logic analysers.”
- How many patents are filed under CPC G06F11/25 (Testing of logic operation, e.g. by logic analysers)?
- Our database includes 146 publications tagged with this CPC code.
- Is patent activity under CPC G06F11/25 growing?
- Publication counts under this code: 8 in 2024 vs 3 in 2025 (latest complete years).