Apparatus and methods for logic analysis to detect trigger conditions relating to data handling transactions in systems using transaction identifiers

US10061671B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-10061671-B2
Application numberUS-201514684558-A
CountryUS
Kind codeB2
Filing dateApr 13, 2015
Priority dateApr 13, 2015
Publication dateAug 28, 2018
Grant dateAug 28, 2018

How to read this patent

A practical reading order for non-experts. Skip the full description unless you need deep technical detail.

  1. Title

    What the patent document calls the invention.

  2. Abstract

    A short plain-language summary of the technical disclosure.

  3. Assignees and inventors

    Who owns or filed the patent and who is credited as inventor.

  4. Key dates

    Filing, priority, publication, and grant dates set the timeline.

  5. First independent claim

    The legal scope of protection — read this for what is actually claimed.

  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

    Prior art links and similar publications in this corpus.

Abstract

Official abstract text for this publication.

Apparatus comprising logic analyzer circuitry comprises a succession of two or more successive trigger condition detectors each configured to detect a match between a respective trigger condition and data handling activity relating to data handling transactions each having a respective transaction identifier; the succession of trigger condition detectors being configured so that a detection by a trigger condition detector of a match with its respective trigger condition enables a next trigger condition detector in the succession to initiate detection of a match with the respective trigger condition of that next trigger condition detector; and a transaction identifier detector associated with a first trigger condition detector in the succession, configured to detect the transaction identifier relating to a data handling transaction for which a match is detected by the first trigger condition detector, and to supply the detected transaction identifier to a subsequent trigger condition detector in the succession of trigger condition detectors; in which the subsequent trigger condition detector is configured to apply the detected transaction identifier as at least a part of its respective trigger condition so as to detect a match only in respect of a data handling transaction having that transaction identifier.

First claim

Opening claim text (preview).

I claim: 1. Apparatus comprising logic analyser circuitry, the logic analyser circuitry comprising: a succession of two or more successive trigger condition detectors; each of said succession of two or more successive trigger condition detectors being configured to detect a match between a respective trigger condition and data handling activity relating to data handling transactions, in which each of the data handling transactions is a transaction between data handling nodes linked by interconnect circuitry; each data handling transaction having a respective transaction identifier; the succession of trigger condition detectors being configured so that a detection by a trigger condition detector of a match with its respective trigger condition enables a next trigger condition detector in the succession to initiate detection of a match with the respective trigger condition of said next trigger condition detector; and a transaction identifier detector associated with a first trigger condition detector in the succession and configured to detect a transaction identifier relating to a data handling transaction for which a match is detected by the first trigger condition detector, the data handling transaction relating to the detected transaction identifier having a respective trigger condition, and to supply the detected transaction identifier to a subsequent trigger condition detector in the succession of trigger condition detectors; in which: the subsequent trigger condition detector is configured to apply the detected transaction identifier as at least a part of its respective trigger condition so as to detect a match only in respect of a data handling transaction having the transaction identifier; one of the data handling nodes comprises a memory; each of the data handling transactions is an access to the memory; a data handling node initiating a data handling transaction is configured to assign a node-specific transaction identifier to the transaction; and the interconnect circuitry is configured to apply a mapping between a node-specific transaction identifier and a respective interconnect transaction identifier which is unique among all pending transactions being handled via the interconnect circuitry. 2. Apparatus according to claim 1 , comprising a trace data generator configured to generate trace data indicative of a data handling transaction for which at least one of the trigger condition detectors detected a match. 3. A diagnostic apparatus comprising: an input module configured to receive a stream of trace data from the apparatus according to claim 2 ; and a data processing element configured to process the trace data. 4. Apparatus according to claim 2 , in which the trace data generator is configured to generate trace data indicative of a data handling transaction for which a last one in the succession of trigger condition detectors detected a match. 5. Apparatus according to claim 1 , in which at least one of the trigger conditions is dependent upon information present on an address bus in respect of a data handling transaction. 6. Apparatus according to claim 1 , in which at least one of the trigger conditions is dependent upon information present on a data bus in respect of a data handling transaction. 7. Apparatus according to claim 1 , in which the subsequent trigger condition detector is a next trigger condition detector. 8. Apparatus according to claim 7 , in which the transaction identifier detector is configured to detect the interconnect transaction identifier. 9. Data processing apparatus comprising: apparatus according to claim 1 ; in which the apparatus comprising logic analyser circuitry is configured to detect matches with trigger conditions in respect of data handling activity relating to data handling transactions between the data handling nodes via the interconnect circuitry. 10. Apparatus comprising logic analyser circuitry, the logic analyser circuitry comprising: a succession of two or more successive trigger condition detection means for detecting a match between a respective trigger condition and data handling activity relating to data handling transactions, in which each of the data handling transactions is a transaction between data handling means linked by interconnect means; each data handling transaction having a respective transaction identifier; the succession of trigger condition detection means being operable so that a detection, by a trigger condition detection means, of a match with its respective trigger condition enables a next trigger condition detection means in the succession to initiate detection of a match with the respective trigger condition of said next trigger condition detection means; and a transaction identifier detection means associated with a first trigger condition detection means in the succession, configured to detect a transaction identifier relating to a data handling transaction for which a match is detected by the first trigger condition detection means, the data handling transaction relating to the detected transaction identifier having a respective trigger condition, and to supply the detected transaction identifier to a subsequent trigger condition detection means in the succession of trigger condition detection means; in which: the subsequent trigger condition detection means is configured to apply the detected transaction identifier as at least a part of its respective trigger condition so as to detect a match only in respect of a data handling transaction having the transaction identifier; one of the data handling means comprises a memory means; each of the data handling transactions is an access to the memory means; a data handling means initiating a data handling transaction is operable to assign a node-specific transaction identifier to the transaction; and the interconnect means is configured to apply a mapping between a node-specific transaction identifier and a respective interconnect transaction identifier which is unique among all pending transactions being handled via the interconnect means. 11. A method of logic analysis, the method comprising a data handling node initiating a data handling transaction, being a transaction between data handling nodes linked by interconnect circuitry, one of the data handling nodes comprising a memory; the data handling node assigning a node-specific transaction identifier to the transaction; the interconnect circuitry applying a mapping between a node-specific transaction identifier and a respective interconnect transaction identifier which is unique among all pending transactions being handled via the interconnect circuitry; detecting a match between a trigger condition and data handling activity relating to data handling transactions; detecting the interconnect transaction identifier relating to a data handling transaction for which the match is detected; supplying the detected interconnect transaction identifier to a subsequent trigger condition detection stage in a succession of trigger condition detections, the subsequent trigger condition detection stage applying the detected interconnect transaction identifier as at least a part of a respective trigger condition so as to detect a match only in respect of a data handling transaction having the interconnect transaction identifier; and in response to detection of a match, enabling a next stage in the succession of trigger condition detections to detect a match with a next trigger condition. 12. A method according to claim 11 , comprising: generating trace data indicative of a data handling transaction for which at least one of the trigger condition detectors detected a matc

Assignees

Inventors

Classifications

  • Built-in tests · CPC title

  • Performance evaluation by tracing or monitoring · CPC title

  • G06F11/25Primary

    Testing of logic operation, e.g. by logic analysers · CPC title

  • G06F11/364Primary

    tracing values on a bus · CPC title

  • Monitoring of transactions · CPC title

Patent family

Related publications grouped by family.

External sources

Frequently asked questions

Answers are generated from the same data shown on this page.

What does patent US10061671B2 cover?
Apparatus comprising logic analyzer circuitry comprises a succession of two or more successive trigger condition detectors each configured to detect a match between a respective trigger condition and data handling activity relating to data handling transactions each having a respective transaction identifier; the succession of trigger condition detectors being configured so that a detection by …
Who is the assignee on this patent?
Advanced Risc Mach Ltd
What technology area does this patent fall under?
Primary CPC classification G06F11/25. Mapped technology areas include Physics.
When was this patent published?
Publication date Tue Aug 28 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).