Efficient resolution of latch race conditions in emulation

Patent metadata

Field	Value
Publication number	US-10140413-B2
Application number	US-201514863843-A
Country	US
Kind code	B2
Filing date	Sep 24, 2015
Priority date	Apr 21, 2015
Publication date	Nov 27, 2018
Grant date	Nov 27, 2018

Abstract

A computer-implemented method for configuring a hardware verification system is presented. The method includes receiving, in the computer, a first code representing a first design including a first latch configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system. The method further includes changing, using the computer, the first code into a second code representing a second design, the changing further including transforming, using the computer, the first latch into a second latch configured to be evaluated in accordance with a second signal different from the first signal after the first signal is received at the second latch, when the second code for the second design is compiled for programming into the hardware verification system.

First claim

What is claimed is:

1. A computer-implemented method for configuring a hardware verification system, the method comprising:
receiving, in the computer, a first code representing a first circuit design including a first latch associated with a potential race condition, the first latch including:
one or more data input signals; and
a first output configured to be evaluated in accordance with a first signal, when the computer is invoked to configure the verification system; and

changing, using the computer, the first code into a second code representing a second circuit design, the changing further including:
transforming, using the computer, the first latch into a second latch without adding an additional data input signal, the second latch having:
the same one or more data input signals as the first latch; and
the first output configured to be evaluated in accordance with a second signal different from the first signal after the first signal is received at the second latch thereby to resolve the potential race condition, when the second code for the second design is compiled and programmed into the hardware verification system.

2. The computer-implemented method of claim 1 , wherein the transforming further comprises configuring, using the computer, the hardware verification system to:
disable evaluation of the second latch for a predetermined period of time using the second signal;
inject a new value of the first signal in the second design after the second latch is disabled; and
enable evaluation of the second latch in accordance with the first signal and the second signal after the expiration of the predetermined period.

3. The computer-implemented method of claim 2 , wherein to disable further comprises receiving the predetermined period when the second code is compiled, using the computer.

4. The computer-implemented method of claim 2 , wherein the predetermined period is associated with an estimated propagation of the first signal to the second latch in the hardware verification system.

5. The computer-implemented method of claim 2 , wherein the transforming further comprises introducing, using the computer, in the second design a state machine configured to realize a number of cycles of a master clock of the hardware verification system within the predetermined period.

6. The computer-implemented method of claim 5 , wherein the transforming further comprises storing the number of cycles of the master clock in the state machine in the hardware verification system after running the hardware verification system.

7. The computer-implemented method of claim 1 , wherein the transforming further comprises configuring, using the computer, the hardware verification system to inject the first signal into the second design after the second signal is received at the second latch.

8. The computer-implemented method of claim 1 , wherein the first latch is one of a plurality of first latches represented in the first code and the second latch is one of a plurality of second latches represented in the second code, wherein the transforming further comprises:
transforming, using the computer, each one of the plurality of first latches into a different corresponding one of the plurality of second latches; and
configuring, using the computer, each one of the plurality of second latches to be evaluated in accordance with the second signal after the first signal is received at each of the plurality of second latches.

9. The computer-implemented method of claim 8 , wherein each one of the plurality of second latches is compiled, using the computer, so as to be programmed in the same programmable device.

10. The computer-implemented method of claim 1 , wherein the evaluation of the second latch is in accordance with the logical AND operation of the first signal and the second signal.

11. The computer-implemented method of claim 1 , wherein the hardware verification system includes a programmable device and the second design is compiled, using the computer, in accordance with the programmable device.

12. The computer-implemented method of claim 1 , wherein the programmable device is a field programmable gate array.

13. The computer-implemented method of claim 1 , wherein the hardware verification system is an emulator system.

14. The computer-implemented method of claim 1 , wherein the hardware verification system is a prototyping system.

15. A system for configuring a hardware verification system, the system configured to:
receive a first code representing a first circuit design including a first latch associated with a potential race condition, the first latch including:
one or more data input signals; and
a first output to be evaluated in accordance with a first signal, when the system is invoked to configure the verification system; and

change the first code into a second code representing a second circuit design, the change further configures the system to:
transform the first latch into a second latch without adding an additional data input signal, the second latch having:
the same one or more data input signals as the first latch; and
the first output configured to be evaluated in accordance with a second signal different from the first signal after the first signal is received at the second latch thereby to resolve the potential race condition, when the second code for the second design is compiled and programmed into the hardware verification system.

16. The system of claim 15 further configured to:
disable evaluation of the second latch for a predetermined period of time using the second signal;
inject a new value of the first signal in the second design after the second latch is disabled; and
enable evaluation of the second latch in accordance with the first signal and the second signal after the expiration of the predetermined period.

17. The system of claim 16 further configured to receive the predetermined period when the second code is compiled.

18. The system of claim 16 , wherein the predetermined period is associated with an estimated propagation of the first signal to the second latch in the hardware verification system.

19. The system of claim 16 further configured to introduce in the second design a state machine configured to realize a number of cycles of a master clock of the hardware verification system within the predetermined period.

20. The system of claim 19 further configured to store the number of cycles of the master clock in the state machine in the hardware verification system after running the hardware verification system.

21. The system of claim 15 further configured to inject the first signal into the second design after the second signal is received at the second latch.

22. The system of claim 15 , wherein the first latch is one of a plurality of first latches represented in the first code and the second latch is one of a plurality of second latches represented in the second code, the system further configured to:
transform each one of the plurality of first latches into a different corresponding one of the plurality of second latches; and
configure each one of the plurality of second latches to be evaluated in accordance with the second signal after the first signal is received at each of the plurality of second latches.

23. The system of claim 22 further configured to compile each one of the plurality of second latches so as to be programmed in the same programmable device.

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Assignees

• Synopsys Inc

Inventors

• Rabinovitch Alexander
• Guerin Xavier

Classifications

• G06F30/398 Primary

  Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] (optical proximity correction [OPC] design processes G03F1/36) · CPC title

• G06F30/331

  with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation · CPC title

• G06F11/25

  Testing of logic operation, e.g. by logic analysers · CPC title

• G06F30/30

  Circuit design · CPC title

• G06F30/34

  for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD] · CPC title