Memory controller with phase adjusted clock for performing memory operations
US-9378786-B2 · Jun 28, 2016 · US
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Shaeffer Ian P patents
Shaeffer Ian P holds 4 patents in our database, with recent filings and technology areas summarized below.
| Metric | Value |
|---|---|
| Total patents | 4 |
| Recent patents | 0 |
| First publication | Dec 1, 2015 |
| Latest publication | Jun 28, 2016 |
Filing trend
Year-over-year patent counts for this assignee.
Recent patents
Latest publications where this party is an assignee.
Memory with deferred fractional row activation
US-9330735-B2 · May 3, 2016 · US
Memory system for error detection and correction coverage
US-9218243-B2 · Dec 22, 2015 · US
Clock generation for timing communications with ranks of memory devices
US-9201444-B2 · Dec 1, 2015 · US
Notable patents
Representative or frequently cited publications from precomputed assignee stats.
Memory controller with phase adjusted clock for performing memory operations
US-9378786-B2 · Jun 28, 2016 · US
Memory with deferred fractional row activation
US-9330735-B2 · May 3, 2016 · US
Memory system for error detection and correction coverage
US-9218243-B2 · Dec 22, 2015 · US
Clock generation for timing communications with ranks of memory devices
US-9201444-B2 · Dec 1, 2015 · US
Top CPC classifications
Most common classification codes in this portfolio.
Technology areas
Mapped technology topics for this assignee.
| Technology | Patents |
|---|---|
| Physics | 4 |
| Electricity | 1 |