Memory controller with phase adjusted clock for performing memory operations

Patent metadata

Field	Value
Publication number	US-9378786-B2
Application number	US-201214111857-A
Country	US
Kind code	B2
Filing date	Apr 18, 2012
Priority date	Apr 18, 2011
Publication date	Jun 28, 2016
Grant date	Jun 28, 2016

Abstract

In an illustrative embodiment, the memory circuit includes first and second data paths on which data is transferred for read and write memory operations and first and second mixer circuits for adjusting the phase of clock signals applied to their inputs. The mixer circuits are cross-coupled so that the outputs of the first and second mixers are both available to both the first and second data paths. One mixer is used to provide a first phase adjusted clock signal for use by the operating circuit and the other mixer is used to provide a second phase adjusted clock signal for use by a following operation whatever that may be.

First claim

What is claimed is:

1. Apparatus comprising:
a pad for coupling the apparatus to a bidirectional data bus supporting data transfer with one or more memory devices separate from the apparatus;
a read data path on which data is transferred for read memory operations with the one or more memory devices via the pad;
a write data path on which data is transferred for write memory operations with the one or more memory devices via the pad;
a first phase adjustment circuit having at least one first clock input to receive at least one clock signal and at least one first clock output to output a first phase adjusted clock signal;
a second phase adjustment circuit having at least one second clock input to receive at least one clock signal and at least one second clock output to output a second phase adjusted clock signal; and
a cross coupler to selectively couple one of the first clock output and the second clock output to either the read data path or the write data path during a first memory operation and to selectively couple the other of the first clock output and the second clock output to either the read data path or the write data path during a second memory operation following the first memory operation.

2. The apparatus of claim 1 wherein the cross coupler includes at least one multiplexer each having inputs coupled to the first and second clock outputs.

3. The apparatus of claim 1 further comprising a clock signal generator for supplying at least one clock signal to each phase adjustment circuit.

4. The apparatus of claim 1 wherein the apparatus is a memory controller for controlling memory devices organized in different ranks.

5. The apparatus of claim 1 wherein the cross coupler selectively couples the first clock output and the second clock output to the read data path and the write data path, respectively, during a first memory operation and coupling the first clock output and the second clock output to the write data path and the read data path, respectively, during a second memory operation following the first memory operation.

6. A memory controller for controlling memory devices organized in ranks, including a first rank and a second rank, the memory controller comprising:
a receiver circuit to receive read data from the memory devices, wherein the receiver circuit receives read data from the first rank via a pad and receives read data from the second rank via the pad;
a first phase adjustment circuit for adjusting a phase of a clock signal to produce a first phase adjusted clock signal;
a second phase adjustment circuit for adjusting a phase of a clock signal to produce a second phase adjusted clock signal; and
wherein, during two consecutive first and second read operations involving first and second ranks, respectively, the memory controller is configured to couple the first phase adjusted clock signal to the receiver circuit during the first read operation and to couple the second phase adjusted clock signal to the receiver circuit during the second read operation.

7. The memory controller of claim 6 wherein the memory controller further comprises a switch having inputs to receive the first phase adjusted clock signal and the second phase adjusted clock signal.

8. The memory controller of claim 6 further comprising a clock signal generator for supplying at least one clock signal to each phase adjustment circuit.

9. The memory controller of claim 6 wherein the first phase adjusted clock signal is used to time transferring of data by the receiver circuit during the first read operation and the second phase adjusted clock signal is used to time transferring of data by the receiver circuit during the second read operation.

10. The memory controller of claim 6 , wherein the memory controller comprises:
a cross-coupling circuit to selectively couple the first phase adjusted clock signal to the receiver circuit during the first read operation and to selectively couple the second phase adjusted clock signal to the receiver circuit instead of the first phase adjusted clock signal during the second read operation.

11. A memory controller for controlling memory devices organized in ranks, including a first rank and a second rank, the memory controller comprising:
a transmitter circuit to transmit write data to the memory devices, wherein the transmitter circuit transmits write data to the first rank via a pad and transmits write data to the second rank via the pad;
a first phase adjustment circuit for adjusting a phase of a clock signal to produce a first phase adjusted clock signal;
a second phase adjustment circuit for adjusting a phase of a clock signal to produce a second phase adjusted clock signal; and
wherein, during two consecutive first and second write operations involving first and second ranks, respectively, the memory controller is configured to couple the first phase adjusted clock signal to the transmitter circuit during the first write operation and to couple the second phase adjusted clock signal to the transmitter circuit during the second write operation.

12. The memory controller of claim 11 , wherein the memory controller comprises:
a cross-coupling circuit to selectively couple the first phase adjusted clock signal to the transmitter circuit during the first write operation and to selectively couple the second phase adjusted clock signal to the transmitter circuit instead of the first phase adjusted clock signal during the second write operation.

13. A method of operating a memory controller coupled via signal conductors to memory devices organized in ranks, including a first rank and a second rank, the method comprising:
generating a first phase adjusted clock signal from at least one clock signal;
generating a second phase adjusted clock signal from the at least one clock signal; and
performing two consecutive first and second memory read accesses involving the first and second ranks, respectively, wherein, during the first memory read access, the memory controller receives data from a memory device in the first rank via a pad and one of the signal conductors according to the first phase adjusted clock signal and wherein, during the second memory read access, the memory controller receives data from a memory device in the second rank via the pad and the same one of the signal conductors according to the second phase adjusted clock signal.

14. The method of claim 13 further comprising between the first and second memory read accesses switching a cross coupler that couples the first and second phase adjusted clock signals to a receiver circuit coupled to one of the signal conductors.

15. The method of claim 14 wherein the cross coupler comprises a multiplexer having inputs to receive the first and second phase adjusted clock signals.

16. The method of claim 13 further comprising:
supplying the at least one clock signal to phase adjustment circuits that generate the first and second phase adjusted clock signals.

Assignees

• Shaeffer Ian P
• Luo Lei
• Rambus Inc

Inventors

• Shaeffer Ian P
• Luo Lei

Classifications

• G11C7/22 Primary

  Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management · CPC title

• G06F13/16

  for access to memory bus (G06F13/28 takes precedence) · CPC title

• G06F13/4243 Primary

  with synchronous protocol · CPC title

• G06F13/4068

  Electrical coupling · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title