Clock generation for timing communications with ranks of memory devices

Patent metadata

Field	Value
Publication number	US-9201444-B2
Application number	US-201113990370-A
Country	US
Kind code	B2
Filing date	Nov 9, 2011
Priority date	Nov 29, 2010
Publication date	Dec 1, 2015
Grant date	Dec 1, 2015

Abstract

A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

First claim

What is claimed is:

1. A memory controller to control a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank, comprising:
a clock generator to generate a first clock signal; and
a timing circuit to generate a second clock signal to time communications with the second memory device, the timing circuit to generate the second clock signal by adjusting a phase of the first clock signal based on calibration data associated with the second memory device and feedback from at least the first memory device.

2. The memory controller of claim 1 , wherein the feedback is from both the first memory device and the second memory device.

3. The memory controller of claim 1 , wherein the memory controller includes edge tracking circuitry to generate timing adjustment data associated with respective memory devices based on feedback from the respective memory devices, the timing adjustment data associated with the second memory device to be used to update the calibration data associated with the second memory device.

4. The memory controller of claim 1 , wherein the timing circuit comprises:
a first phase adjuster to adjust the phase of the first clock signal; and
a plurality of respective storage elements, each to store calibration data associated with a respective memory device in a respective rank, wherein one of the respective storage elements is to store the calibration data associated with the second memory device;
wherein the first phase adjuster is to be selectively coupled to the storage element storing the calibration data associated with the second memory device when the second clock signal is being generated to time communication with the second memory device, the first phase adjuster to adjust the phase of the first clock signal based on the calibration data stored in the selectively coupled storage element.

5. The memory controller of claim 4 , further comprising:
calibration circuitry to perform calibration for the first memory device and, in response, to determine an amount by which to adjust calibration data associated with the first memory device in a first storage element of the plurality of storage elements; and
adjustment circuitry to adjust calibration data associated with the second memory device in a second storage element by the determined amount.

6. The memory controller of claim 5 , wherein the adjustment circuitry is to adjust calibration data in each respective storage element by the determined amount.

7. The memory controller of claim 4 , wherein:
the first phase adjuster is to generate an intermediate clock signal by adjusting the phase of the first clock signal; and
the timing circuit further comprises a second phase adjuster to generate the second clock signal by adjusting a phase of the intermediate clock signal based on the timing adjustment data derived from the feedback.

8. The memory controller of claim 7 , wherein the second phase adjuster is to operate using values of the timing adjustment data associated with communicating with the first memory device during communication with the first memory device, and to continue to operate using a value of the timing adjustment data associated with communicating with the first memory device initially after the memory controller transitions from communicating with the first memory device to the second memory device.

9. The memory controller of claim 7 , wherein the second phase adjuster comprises a digitally controlled delay line.

10. The memory controller of claim 1 , further comprising a transmitter, coupled to the timing circuit, to transmit data to any of the plurality of memory devices in the respective ranks in accordance with the second clock signal.

11. The memory controller of claim 1 , further comprising a sampling circuit, coupled to the timing circuit, to sample data from any of the plurality of memory devices in the respective ranks in accordance with the second clock signal.

12. A memory controller, comprising:
a clock generator to generate a first clock signal; and
a timing circuit to generate a second clock signal from the first clock signal to time communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank, the timing circuit comprising:
a first phase adjuster to generate an intermediate clock signal by adjusting a phase of the first clock signal;
a plurality of respective storage elements, each to store calibration data associated with a respective memory device in a respective rank and configured to be selectively coupled to the first phase adjuster when the memory controller is to communicate with the respective memory device in the respective rank, wherein the first phase adjuster is to adjust the phase of the first clock signal based on the calibration data stored in the selectively coupled storage element; and
a second phase adjuster to generate the second clock signal by adjusting a phase of the intermediate clock signal based on timing adjustment data associated with feedback from one or more of the plurality of memory devices in the respective ranks.

13. A memory controller, comprising:
a clock generator to generate a first clock signal;
a first phase adjuster to generate a second clock signal by adjusting a phase of the first clock signal, the second clock signal to time communications with any of a plurality of memory devices in respective ranks;
a plurality of respective storage elements, each to store calibration data associated with a respective memory device in a respective rank and configured to be selectively coupled to the first phase adjuster when the memory controller is to communicate with the respective memory device in the respective rank, wherein the first phase adjuster is to adjust the phase of the first clock signal based on the calibration data stored in the selectively coupled storage element;
calibration circuitry to perform calibration for a first memory device in a first rank and, in response, to determine an amount by which to adjust calibration data associated with the first memory device in a first storage element of the plurality of storage elements; and
adjustment circuitry to adjust calibration data associated with the second memory device in a second storage element of the plurality of respective storage elements by the determined amount.

14. A method of controlling memory devices, comprising:
at a memory controller coupled to memory devices in a plurality of ranks, including a first memory device in a first rank and a second memory device in a second rank:
generating a first clock signal;
adjusting a phase of the first clock signal to generate a second clock signal, the adjusting based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device; and
timing communications with the second memory device, in accordance with the second clock signal.

15. The method of claim 14 , further comprising:
determining an amount to adjust calibration data associated with the first memory device, based on feedback from the first memory device;
adjusting the calibration data associated with the first memory device by the determined amount; and
adjusting the calibration data associated with the second memory device by the determined amount;
wherein the adjusting of the phase of the first clock signal is based at least in part on the adjusted calibration data associated with the second memory device.

Assignees

• Zerbe Jared L
• Shaeffer Ian P
• Eble John
• Rambus Inc

Inventors

• Zerbe Jared L
• Shaeffer Ian P
• Eble John

Classifications

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G11C7/222

  Clock generating, synchronizing or distributing circuits within memory device · CPC title

• G11C7/04

  with means for avoiding disturbances due to temperature effects · CPC title

• G06F1/04 Primary

  Generating or distributing clock signals or signals derived directly therefrom · CPC title

• G06F1/10

  Distribution of clock signals {, e.g. skew} · CPC title