Method for reducing execution jitter in multi-core processors within an information handling system

Patent metadata

Field	Value
Publication number	US-RE49781-E
Application number	US-202016817238-A
Country	US
Kind code	E1
Filing date	Mar 12, 2020
Priority date	Oct 16, 2012
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled. If none of the cores is selected to be disabled, the control logic determines if a second set of cores is selected to be jitter controlled. If the second set of cores is selected to be jitter controlled, the second set of cores is set to a first operating state. If the first set of cores is selected to be disabled, the control logic determines a second operating state for a third set of enabled cores. The control logic determines if the third set of enabled cores is jitter controlled, and if the third set of enabled cores is jitter controlled, the control logic sets the third set of enabled cores to the second operating state.

First claim

What is claimed is:

1. A computer implemented method of reducing execution jitter within a processor having a control logic and a plurality of individual cores, the method comprising:
receiving at least one core configuration parameter;
determining from the at least one core configuration parameter if a first set of one or more cores is selected to be disabled from operation;
in response to none of the first set of cores being selected to be disabled,:
determining if a second set of one or more cores is selected to be jitter controlled; and
in response to the second set of cores being selected to be jitter controlled, setting the second set of cores to a first operating state that reduces jitter; and

in response to the first set of cores being selected to be disabled,:
disabling the first set of cores, determining if a third set of one or more enabled cores is selected to be jitter contolled, and;
determining a second operating state that reduces jitter for the a third set of one or more enabled cores;
determining if the third set of cores is selected to be jitter controlled; and
in response to the third set of enabled cores being selected to be jitter controlled, setting the third set of enabled cores to the second operating state that reduces jitter.

2. The method of claim 1 , wherein the at least one core configuration parameter comprises an ordered lookup table of the third set of enabled cores.

3. The method of claim 1 , further comprising:
receiving the at least one core configuration parameter from a basic input output system stored in memory; and
loading the at least one core configuration parameter into the control logic.

4. The method of claim 1 , wherein the first operating state comprises a first operating frequency for the second set of cores and the second operating state comprises a second operating frequency for the third set of cores, and wherein the second operating state is based on the number of disabled cores.

5. The method of claim 1 , wherein the disabled cores do not operate and are selected to be disabled based on a physical location of each core.

6. The method of claim 1 , further comprising:
determining a third operating state for a fourth set of enabled cores;
determining if the fourth set of enabled cores are selected to be jitter controlled; and
in response to the fourth set of enabled cores selected to be jitter controlled, setting the fourth set of enabled cores to the third operating state.

7. The method of claim 1 , further comprising:
loading, into the control logic, an ordered lookup table of the cores ordered by maximum physical spacing between each pair of sequentially enabled cores among a sequence of enabled cores;
enabling operation of a first core in the ordered lookup table;
determining if all of the third set of enabled cores have been enabled for operation; and
in response to all of the third set of enabled cores not being having been enabled, enabling operation of a next sequential core in the ordered lookup table.

8. The method of claim 1 , further comprising:
selecting a first core of the plurality of cores;
placing the first core in a first position in an ordered lookup table;
determining if all of the cores have been placed in the lookup table; and
in response to all of the cores not having been placed in the table, selecting a second core with maximum spacing from the other cores that are not yet selected for the table and placing the selected second core in a next sequential position in the ordered lookup table.

9. A multi-core processor, comprising:
a plurality of cores in communication; and
control logic in communication with the plurality of cores and having firmware executing thereon, wherein execution of the firmware configures the control logic to:
receive at least one core configuration parameter;
determine from the at least one core configuration parameter if a first set of one or more cores are is selected to be disabled from operation;
in response to none of the first set of cores being selected to be disabled,;
determine if a second set of one or more cores are is selected to be jitter controlled; and
in response to the second set of the cores being selected to be jitter controlled, set the second set of cores to a first operating state that reduces jitter; and

in response to the first set of cores being selected to be disabled,;
disable the first set of cores from operation based on a physical location of each coreand;
determine a second operating state that reduces jitter for a third set of one or more enabled cores;
determine if the third set of enabled cores are is selected to be jitter controlled; and
in response to the third set of enabled cores being selected to be jitter controlled, set the third set of enabled cores to the second operating state that reduces jitter.

10. The multi-core processor of claim 9 , further comprising wherein upon execution of the firmware, the control logic that receives the at least one core configuration parameter, and wherein the at least one core configuration parameter comprises an ordered lookup table of the third set of enabled cores.

11. The multi-core processor of claim 9 , further comprising logic that wherein upon execution of the firmware, the control logic:
receives the at least one core configuration parameter in a basic input output system memory; and
loads the at least one core configuration parameter into the control logic.

12. The multi-core processor of claim 9 , wherein the first operating state comprises a first operating frequency for the second set of cores and the second operating state comprises a second operating frequency for the third set of cores, and wherein the second operating state is based on the number of disabled cores.

13. The multi-core processor of claim 9 , further comprising logic that wherein upon execution of the firmware, the control logic:
determines a third operating state for a fourth set of enabled cores;
determines if the fourth set of enabled cores are selected to be jitter controlled; and
in response to the fourth set of enabled cores selected to be jitter controlled, sets the fourth set of enabled cores to the third operating state.

14. The multi-core processor of claim 9 , further comprising logic that wherein upon execution of the firmware, the control logic:
loads an ordered lookup table of the cores ordered by maximum spacing into the control logic;
enables a first core in the ordered lookup table;
determines if all of the third set of enabled cores have been enabled for operation; and
in response to all of the third set of enabled cores not having been enabled, enables a subsequent second core in the ordered lookup table.

15. The multi-core processor of claim 9 , further comprising logic that wherein upon execution of the firmware, the control logic:
selects a first core of the plurality of cores;
places the first core in a first position in an ordered lookup table;
determines if all of the cores have been placed in the lookup table; and
in response to all of the cores not having been placed in the table, selects a second core with maximum spacing from the other cores and placing places the selected second core in a second position in the ordered lookup table.

16. An information handling system Information Handling System (IHS), comprising:
a processor having a plurality of cores and a control logic; and
a memory coupled to the processor via a system interconnect, the control logic having firmware executing thereon to reduce execution jitter, wherein e

Assignees

• Dell Products Lp

Inventors

• Molloy Michael Karl
• Khatri Mukund P
• Hormuth Robert Wayne

Classifications

• G06F9/223 Primary

  Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems · CPC title

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title