Workload optimized server for intelligent algorithm trading platforms

Patent metadata

Field	Value
Publication number	US-9619289-B2
Application number	US-201414483597-A
Country	US
Kind code	B2
Filing date	Sep 11, 2014
Priority date	Sep 11, 2014
Publication date	Apr 11, 2017
Grant date	Apr 11, 2017

Abstract

Systems and methods for a workload optimized server for intelligent algorithm trading platforms. In an illustrative, non-limiting embodiment, an Information Handling System (IHS) may include a plurality of Central Processing Units (CPUs) and a control circuit coupled to the plurality of CPUs, the control circuit having a memory configured to store program instructions that, upon execution by the control logic, cause the IHS to: set a first number of enabled cores in a first CPU to operate with a first all-core turbo frequency, and set a second number of enabled cores in a second CPU to operate with a second all-core turbo frequency, where the first number of enabled cores is different from the second number of enabled cores, and where at least one of the first or second all core turbo frequencies is selected to cause the IHS to operate with reduced execution jitter.

First claim

The invention claimed is:

1. An Information Handling System (IHS), comprising:
a plurality of Central Processing Units (CPUs); and
a control circuit coupled to the plurality of CPUs, the control circuit having a memory configured to store program instructions that, upon execution by the control logic, cause the IHS to:
set a first number of enabled cores in a first CPU to operate with a first all-core turbo frequency and set a second number of enabled cores in a second CPU to operate with a second all-core turbo frequency, wherein the first number of enabled cores is different from the second number of enabled cores, and wherein at least one of the first or second all core turbo frequencies is selected to cause the IHS to operate with reduced execution jitter.

2. The IHS of claim 1 , wherein the control circuit includes basic input output (BIOS) logic, wherein a first portion of an application is run by the first CPU, and wherein a second portion of the application is run by the second CPU.

3. The IHS of claim 2 , wherein the first portion of the application includes frequency sensitive threads and wherein the second portion of application includes parallel execution sensitive threads.

4. The IHS of claim 3 , wherein the application includes a high frequency trading application, wherein the first portion includes a feed handling and/or trading platform, and wherein the second portion includes an analytics platform.

5. The IHS of claim 1 , wherein the first number of enabled cores is smaller than the second number of enabled cores, and wherein the first all-core turbo frequency is greater than the second all-core turbo frequency.

6. The IHS of claim 1 , wherein the program instructions, upon execution by the control logic, further cause the IHS to select the first and second all-core turbo frequencies using a turbo boost frequency table.

7. The IHS of claim 5 , wherein the first all-core turbo frequency is a highest frequency available for the first number of enabled cores in the turbo boost frequency table.

8. The IHS of claim 1 , wherein the program instructions, upon execution by the control logic, further cause the IHS to:
change at least one of the first number of enabled cores or the second number of enabled cores, and change at least one of the first or second all-core turbo frequencies to reduce the execution jitter.

9. The IHS of claim 1 , wherein the program instructions, upon execution by the control logic, further cause the IHS to schedule all Advanced Vector Extensions (AVX) threads on the second CPU instead of the first CPU.

10. A computer-implemented method, comprising:
receiving an indication of: (a) a first number of enabled cores in a first processor of a multi-processor Information Handling System (IHS) chosen to execute a first part of an application; (b) a second number of enabled cores in a second processor of the multi-processor IHS chosen to execute a second part of the application; and (c) a type of instruction to be executed within the first or second parts of the application; and
selecting a first all-core turbo frequency of the first processor and a second all-core turbo frequency of the second processor to reduce an execution jitter of the application during concurrent execution of the first and second portions, the selection based upon the first number of cores, the second number of cores, and the type of instruction.

11. The computer-implemented method of claim 10 , wherein the first and second number of enabled cores are selected by a human user.

12. The computer-implemented method of claim 10 , wherein the application includes a high frequency trading application, wherein the first portion includes a feed handling and/or trading platform, and wherein the second portion includes an analytics platform.

13. The computer-implemented method of claim 10 , wherein the first number of enabled cores is smaller than the second number of enabled cores, and wherein the first all-core turbo frequency is greater than the second all-core turbo frequency.

14. The computer-implemented method of claim 10 , wherein selecting the first and second all-core turbo frequencies includes using a turbo boost frequency table.

15. The computer-implemented method of claim 10 , wherein the first all-core turbo frequency is a highest frequency available for the first number of enabled cores in the turbo boost frequency table.

16. The computer-implemented method of claim 10 , wherein the type of instructions includes an Advanced Vector Extensions (AVX) instruction.

17. A non-transitory computer-readable medium having program instructions stored thereon that, upon execution by an Information Handling System (IHS), cause the IHS to:
receive an indication of a type of instruction to be executed by a first CPU; and
select a first all-core turbo frequency of the first CPU and a second all-core turbo frequency of a second CPU to reduce an execution jitter of an application including one or more instructions of the indicated type, wherein the first all-core turbo frequency is different from the second all-core turbo frequency, and wherein at least one of the first or second CPUs has at least one of its cores disabled.

18. The non-transitory computer-readable medium of claim 17 , wherein the type of instructions includes an Advanced Vector Extensions (AVX) instruction.

19. The non-transitory computer-readable medium of claim 17 , wherein the program instructions, upon execution by the IHS, further cause the IHS to:
receive an indication of a first number of cores in the first CPU chosen to execute a first part of an application and of a second number of cores in the second CPU to execute a second part of the application; and
select the first and second all-core turbo frequencies based, at least in part, upon the first and second number of cores.

20. The non-transitory computer-readable medium of claim 19 , wherein the application includes a high frequency trading application, wherein the first portion includes a feed handling and/or trading platform, and wherein the second portion includes an analytics platform.

Assignees

• Dell Products Lp

Inventors

• Khatri Mukund P

Classifications

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• G06F9/505 Primary

  considering the load · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title

• G06F9/4405

  Initialisation of multiprocessor systems · CPC title