Method for reducing execution jitter in multi-core processors within an information handling system

Patent metadata

Field	Value
Publication number	US-9817660-B2
Application number	US-201514724626-A
Country	US
Kind code	B2
Filing date	May 28, 2015
Priority date	Oct 16, 2012
Publication date	Nov 14, 2017
Grant date	Nov 14, 2017

Abstract

A method of reducing execution jitter includes a processor having several cores and control logic that receives core configuration parameters. Control logic determines if a first set of cores are selected to be disabled. If none of the cores is selected to be disabled, the control logic determines if a second set of cores is selected to be jitter controlled. If the second set of cores is selected to be jitter controlled, the second set of cores is set to a first operating state. If the first set of cores is selected to be disabled, the control logic determines a second operating state for a third set of enabled cores. The control logic determines if the third set of enabled cores is jitter controlled, and if the third set of enabled cores is jitter controlled, the control logic sets the third set of enabled cores to the second operating state.

First claim

What is claimed is:

1. A computer implemented method of reducing execution jitter within a processor having control logic and a plurality of individual cores, the method comprising:
determining from at least one configuration parameter if a first set of one or more cores is selected to be disabled from operation, the plurality of individual cores being configurable as a first set, a second set, and a third set of one or more cores, each set being selectably enabled or disabled, and each set being configurable in at least an operating state that reduces jitter, the operating state being in part based on a number of disabled cores;
in response to the first set of cores being selected to be disabled, disabling the first set of cores and determining an operating state that reduces jitter for the third set of one or more enabled cores, while the first set of one or more cores are disabled;
determining if the third set of enabled cores are selected to be jitter controlled;
in response to the third set of enabled cores being selected to be jitter controlled, setting the third set of enabled cores to the operating state that reduces jitter;
in response to the first set of cores not being selected to be disabled, determining if a second set of one or more cores are selected to be jitter controlled; and
in response to the second set of cores being selected to be jitter controlled, setting the second set of cores to a next operating state that reduces jitter.

2. The method of claim 1 , wherein the core configuration parameter comprises an ordered lookup table of the third set of enabled cores.

3. The method of claim 1 , further comprising:
receiving the core configuration parameter from a basic input output system stored in memory; and
loading the core configuration parameter into the control logic.

4. The method of claim 1 , wherein the next operating state comprises a first operating frequency for the second set of cores and the operating state comprises a second operating frequency for the third set of cores.

5. The method of claim 1 , wherein the disabled cores do not operate and are selected to be disabled based on a physical location of each core.

6. The method of claim 1 , further comprising:
determining a third operating state for a fourth set of enabled cores;
determining if the fourth set of enabled cores are selected to be jitter controlled; and
in response to the fourth set of enabled cores selected to be jitter controlled, setting the fourth set of enabled cores to the third operating state.

7. The method of claim 1 , further comprising:
loading, into the control logic, an ordered lookup table of the cores ordered by maximum physical spacing between each pair of sequentially enabled cores among a sequence of enabled cores;
enabling operation of a first core in the ordered lookup table;
determining if all of the third set of enabled cores have been enabled for operation; and
in response to all of the third set of enabled cores not being enabled, enabling operation of a next sequential core in the ordered lookup table.

8. The method of claim 1 , further comprising:
selecting a first core of the plurality of cores;
placing the first core in a first position in an ordered lookup table;
determining if all of the cores have been placed in the lookup table; and
in response to all of the cores not having been placed in the table, selecting a second core with maximum spacing from the other cores that are not yet selected for the table and placing the selected second core in a next sequential position in the ordered lookup table.

9. A multi-core processor comprising:
a plurality of cores grouped as a first set, a second set, and a third set of one or more cores, each set being selectably enabled or disabled, and each set being configurable in at least one operating state that is based on a number of disabled cores; and
control logic in communication with the plurality of cores and having firmware executing thereon, wherein the firmware configures the control logic to:
determine from at least one configuration parameter if a first set of one or more cores are selected to be disabled from operation;
in response to the first set of cores being selected to be disabled, disable the first set of cores from operation based on a physical location of each core and determine an operating state that reduces jitter for a third set of one or more enabled cores, while the first set of one or more cores are disabled;
determine if the third set of enabled cores are selected to be jitter controlled;
in response to the third set of enabled cores being selected to be jitter controlled, set the third set of enabled cores to the operating state that reduces jitter;
in response to none of the first set of cores being selected to be disabled, determines if a second set of one or more cores are selected to be jitter controlled; and
in response to the second set of the cores being selected to be jitter controlled, set the second set of cores to another operating state that reduces jitter.

10. The multi-core processor of claim 9 , further comprising logic that:
receives the at least one core configuration parameter in a basic input output system memory; and
loads the core configuration parameter into the control logic; and
wherein the core configuration parameter comprises an ordered lookup table of the third set of enabled cores.

11. The multi-core processor of claim 9 , wherein the other operating state comprises a first operating frequency for the second set of cores and the operating state comprises a second operating frequency for the third set of cores, and wherein the operating state is based on the number of disabled cores.

12. The multi-core processor of claim 9 , further comprising logic that:
determines a third operating state for a fourth set of enabled cores;
determines if the fourth set of enabled cores are selected to be jitter controlled; and
in response to the fourth set of enabled cores selected to be jitter controlled, sets the fourth set of enabled cores to the third operating state.

13. The multi-core processor of claim 9 , further comprising logic that:
loads an ordered lookup table of the cores ordered by maximum spacing into the control logic;
enables a first core in the ordered lookup table;
determines if all of the third set of enabled cores have been enabled for operation; and
in response to all of the third set of enabled cores not being enabled, enables a subsequent second core in the ordered lookup table.

14. The multi-core processor of claim 9 , further comprising logic that:
selects a first core of the plurality of cores;
places the first core in a first position in an ordered lookup table;
determines if all of the cores have been placed in the lookup table; and
in response to all of the cores not having been placed in the table, selects a second core with maximum spacing from the other cores and placing the selected second core in a second position in the ordered lookup table.

15. An information handling system comprising:
a processor having a plurality of cores and a control logic, the plurality of cores grouped as a first set, a second set, and a third set of one or more cores, each set being selectably enabled or disabled;
a memory coupled to the processor via a system interconnect;
the control logic having firmware executing thereon to reduce execution jitter, wherein the firmware configures the control logic to:
determine from at least one configuration parameter if the first set of one or more cores are selected to be disabled from operation;
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Assignees

• Dell Products Lp

Inventors

• Molloy Michael Karl
• Khatri Mukund P
• Hormuth Robert W

Classifications

• G06F9/5094 Primary

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• Y02B60/142

  Cross-Sectional Technologies · mapped topic

• G06F9/223 Primary

  Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems · CPC title

• Y02D10/00

  Energy efficient computing, e.g. low power processors, power management or thermal management · CPC title