Method and apparatus improving gate oxide reliability by controlling accumulated charge

Patent metadata

Field	Value
Publication number	US-RE48965-E
Application number	US-201916710998-A
Country	US
Kind code	E1
Filing date	Dec 11, 2019
Priority date	Jul 11, 2005
Publication date	Mar 8, 2022
Grant date	Mar 8, 2022

Abstract

A method and apparatus are disclosed for use in improving the gate oxide reliability of semiconductor-on-insulator (SOI) metal-oxide-silicon field effect transistor (MOSFET) devices using accumulated charge control (ACC) techniques. The method and apparatus are adapted to remove, reduce, or otherwise control accumulated charge in SOI MOSFETs, thereby yielding improvements in FET performance characteristics. In one embodiment, a circuit comprises a MOSFET, operating in an accumulated charge regime, and means for controlling the accumulated charge, operatively coupled to the SOI MOSFET. A first determination is made of the effects of an uncontrolled accumulated charge on time dependent dielectric breakdown (TDDB) of the gate oxide of the SOI MOSFET. A second determination is made of the effects of a controlled accumulated charge on TDDB of the gate oxide of the SOI MOSFET. The SOI MOSFET is adapted to have a selected average time-to-breakdown, responsive to the first and second determinations, and the circuit is operated using techniques for accumulated charge control operatively coupled to the SOI MOSFET. In one embodiment, the accumulated charge control techniques include using an accumulated charge sink operatively coupled to the SOI MOSFET body.

First claim

What is claimed is:

1. An RF switch, comprising:
a first RF port;
a second RF port;
a first switch transistor grouping coupled with the first and second RF ports, and controlled by a first switch control signal, the first switch transistor grouping comprising a first plurality of switch NMOSFETs arranged in a stacked configuration;
a shunt transistor grouping coupled with the first RF port and with ground, and controlled by a shunt control signal, the shunt transistor grouping comprising a plurality of shunt NMOSFETs arranged in a stacked configuration, wherein at least one of the plurality of shunt NMOSFETs comprises a first body and a first accumulated charge sink (ACS) coupled with the first body and configured so that when the at least one shunt NMOSFET is disabled, a first negative bias voltage that is substantially negative with respect to ground applied to the first ACS substantially prevents accumulated charge from accumulating in the first body of the at least one shunt NMOSFET; and
a silicon-on-insulator substrate, wherein the first switch transistor grouping and the shunt transistor grouping are fabricated in a silicon layer of the silicon-on-insulator substrate so that when the first switch transistor grouping is enabled by the first switch control signal and the shunt transistor grouping is disabled by the shunt control signal, a signal on the first RF port is passed through to the second RF port, and when the first switch transistor grouping is disabled by the first switch control signal and the shunt transistor grouping is enabled by the shunt control signal, the signal on the first RF port is grounded.

2. The RF switch of claim 1 , wherein at least one of the first plurality of switch NMOSFETs has a second body and a second accumulated charge sink (ACS) coupled with the second body and configured so that when the at least one switch NMOSFET is disabled, a second negative bias voltage that is substantially negative with respect to ground applied to the second ACS substantially prevents accumulated charge from accumulating in the second body of the at least one switch NMOSFET.

3. The RF switch of claim 2 , wherein the at least one switch NMOSFET includes a gate, and wherein the gate of the at least one switch NMOSFET and the second ACS are coupled together and also coupled with the first switch control signal.

4. The RF switch of claim 2 , wherein the at least one shunt NMOSFET includes a gate, and wherein the gate of the at least one shunt NMOSFET and the first ACS are coupled together and also coupled with the shunt control signal.

5. The RF switch of claim 2 , wherein the at least one switch NMOSFET includes a gate, and wherein a diode is coupled between the at least one switch NMOSFET gate and the second ACS such that the diode prevents current flow into the second body when the at least one switch NMOSFET is enabled.

6. The RF switch of claim 2 , wherein the at least one shunt NMOSFET includes a gate, and wherein a diode is coupled between the at least one shunt NMOSFET gate and the first ACS such that the diode prevents current flow into the first body when the at least one shunt NMOSFET is enabled.

7. The RF switch of claim 2 , wherein the at least one switch NMOSFET includes a gate, and wherein an electrical device is coupled between the gate and the second ACS such that the electrical device prevents current flow into the second body when the at least one switch NMOSFET is enabled.

8. The RF switch of claim 2 , wherein the at least one shunt NMOSFET includes a gate, and wherein an electrical device is coupled between the gate and the first ACS such that the electrical device prevents current flow into the first body when the at least one shunt NMOSFET is enabled.

9. The RF switch of claim 2 , wherein the couplings comprise at least one of the following coupling types: capacitive; inductive; electro-magnetic; and resistive coupling, including a “short” resistive coupling wherein the resistive value of the coupling comprises approximately zero ohms.

10. The RF switch of claim 2 , wherein the first and second negative bias voltages are substantially more negative than the lowest voltage value of ground, a threshold voltage (Vth), a source voltage (Vs), and a drain voltage (Vd).

11. The RF switch of claim 2 , wherein the first and second negative bias voltages are at least one volt more negative than the lowest voltage value of ground, a threshold voltage (Vth), a source voltage (Vs), and a drain voltage (Vd).

12. The RF switch of claim 2 , wherein each NMOSFET has an associated and respective gate voltage Vg, and wherein the associated gate voltage is at least one volt more negative than the lowest voltage value of ground, a threshold voltage (Vth), a source voltage (Vs), and a drain voltage (Vd).

13. The RF switch of claim 2 , further comprising:
a third RF port; and
a second switch transistor grouping coupled with the second and third RF ports wherein the second switch transistor grouping comprises a second plurality of switch NMOSFETs arranged in a stacked configuration, wherein at least one of the second plurality of switch NMOSFETs has a third body and a third accumulated charge sink (ACS) coupled to the third body and configured so that when the at least one switch NMOSFET of the second plurality of switch NMOSFETs is disabled, a third negative bias voltage that is substantially negative with respect to ground applied to the third ACS substantially prevents accumulated charge from accumulating in the third body.

14. The RF switch of claim 13 , wherein preventing accumulated charge from accumulating in the third body of the at least one switch NMOSFET improves linearity of the signal passed through to the second RF port.

15. The RF switch of claim 1 , wherein the shunt transistor grouping comprises at least three NMOSFETs.

16. The RF switch of claim 1 , wherein the shunt transistor grouping comprises at least six NMOSFETs.

17. The RF switch of claim 1 , wherein the shunt transistor grouping comprises at least nine NMOSFETs.

18. The RF switch of claim 2 , wherein the first switch transistor grouping comprises at least three NMOSFETs.

19. The RF switch of claim 2 , wherein the first switch transistor grouping comprises at least six NMOSFETs.

20. The RF switch of claim 2 , wherein the first switch transistor grouping comprises at least nine NMOSFETs.

21. The RF switch of claim 2 , wherein the first switch transistor grouping comprises at least twelve NMOSFETs.

22. The RF switch of claim 2 , wherein the first switch transistor grouping comprises at least fifteen NMOSFETs.

23. The RF switch of claim 13 , wherein the second switch transistor grouping comprises at least three NMOSFETs.

24. The RF switch of claim 13 , wherein the second switch transistor grouping comprises at least six NMOSFETs.

25. The RF switch of claim 13 , wherein the second switch transistor grouping comprises at least nine NMOSFETs.

26. The RF switch of claim 13 , wherein the second transistor grouping comprises at least twelve NMOSFETs.

27. The RF switch of claim 13 , wherein the second switch transistor grouping comprises at least fifteen NMOSFETs.

28. The RF switch of claim 2 , wherein the at least one shunt NMOSFET further comprises an electrical contact region proximate to the first ACS, and wherein the electrical contact region facilitates coupling to the first body.

Assignees

• Psemi Corp

Inventors

• Stuber Michael A
• Brindle Christopher N
• Kelly Dylan J
• Kemerling Clint L
• Imthurn George P
• Welstand Robert B
• Burgener Mark L
• Dribinsky Alexander
• Kim Tae Youn

Classifications

• H10D86/201

  the substrates comprising an insulating layer on a semiconductor body, e.g. SOI (H10D86/40 take precedence) · CPC title

• H10D30/6759

  Silicon-on-sapphire [SOS] substrates · CPC title

• H10D30/6744

  Monocrystalline silicon · CPC title

• H10D30/6743

  Silicon · CPC title

• H10D30/6739

  Conductor-insulator-semiconductor electrodes · CPC title