Stressed substrates for transient electronic systems

Patent metadata

Field	Value
Publication number	US-RE47570-E
Application number	US-201715726944-A
Country	US
Kind code	E1
Filing date	Oct 6, 2017
Priority date	Oct 11, 2013
Publication date	Aug 13, 2019
Grant date	Aug 13, 2019

Abstract

A stressed substrate for transient electronic systems (i.e., electronic systems that visually disappear when triggered to do so) that includes one or more stress-engineered layers that store potential energy in the form of a significant internal stress. An associated trigger mechanism is also provided that, when triggered, causes an initial fracture in the stressed substrate, whereby the fracture energy nearly instantaneously travels throughout the stressed substrate, causing the stressed substrate to shatter into multiple small (e.g., micron-sized) pieces that are difficult to detect. The internal stress is incorporated into the stressed substrate through strategies similar to glass tempering (for example through heat or chemical treatment), or by depositing thin-film layers with large amounts of stress. Patterned fracture features are optionally provided to control the final fractured particle size. Electronic systems built on the substrate are entirely destroyed and dispersed during the transience event.

First claim

The invention claimed is:

1. A transient electronic device comprising:
a stressed substrate including at least one tensile stress layer having a residual tensile stress and at least one compressive stress layer having a residual compressive stress and being operably integrally connected to the at least one tensile stress layer such that the residual tensile and compressive stresses are self-equilibrating; and
a trigger mechanism attached to the stressed substrate and including means for generating configured to generate an initial fracture in said stressed substrate,
wherein said residual tensile and compressive stresses are sufficient to generate secondary fractures in response to said initial fracture that propagate throughout through said stressed substrate, whereby said stressed substrate is powderized.

2. The transient electronic device of claim 1 , further comprising a functional layer including one or more electronic elements, wherein the functional layer is bonded to the stressed substrate such that the secondary fractures propagate into said functional layer, whereby said functional layer is powderized substantially simultaneously with said stressed substrate.

3. The transient electronic device of claim 2 ,
wherein the functional substrate layer comprises silicon, and
wherein the one or more electronic elements are integrally fabricated on the functional layer.

4. The transient electronic device of claim 1 , wherein said stressed substrate further comprises a central, substantially unstressed layer.

5. The transient electronic device of claim 1 , wherein said trigger mechanism comprises one of means for applying resistive heating to is configured to heat said stressed substrate, means for initiating initiate a chemical reaction in said stressed substrate, and means for applying or apply a mechanical pressure to said stressed stressed substrate to generate the initial fracture.

6. The transient electronic device of claim 2 , wherein at least one of said functional layer and said substrate comprises a plurality of patterned fracture features formed such that, when said substrate is powderized by release of said potential energy, said substrate fractures along said plurality of patterned fracture features in response to the initial fracture.

7. The transient electronic device of claim 2 , wherein said functional layer comprises one or more IC chips attached to the stressed substrate layer such that said IC chips are powderized upon release of the potential energy fracture in response to the initial fracture.

8. The transient electronic device of claim 7 , wherein said IC chips are attached to the stressed substrate layer by one of a sealing glass and an anodic bond.

9. The transient electronic device of claim 1 , wherein said functional layer comprises one or more thin-film electronic elements disposed directly on said stressed substrate.

10. A method for manufacturing a transient electronic device comprising:
forming a stressed substrate including at least one tensile stress layer having a residual tensile stress and at least one compressive stress layer having a residual compressive stress and being operably integrally connected to the at least one tensile stress layer such that residual tensile and compressive stresses are self-equilibrating; and
disposing a trigger mechanism configured to generate an initial fracture in the stressed substrate and one or more electronic elements on the stressed substrate.

11. The method of claim 10 , wherein forming stressed substrate comprises depositing one or more substrate materials while varying applied process conditions such that the deposited substrate material forms a plurality of layer portions collectively forming a stress gradient.

12. The method of claim 11 , wherein forming the stressed substrate comprises depositing said one or more substrate materials onto a sacrificial structure and then removing said one or more sacrificial structure.

13. The method of claim 11 , wherein forming stressed substrate comprises depositing said one or more substrate materials onto a core substrate.

14. The method of claim 10 , wherein forming stressed substrate comprises subjecting a core substrate to one of an ion-exchange tempering treatment, a chemical treatment and a thermal treatment.

15. The method of claim 10 , wherein disposing said one or more electronic elements comprises fabricating said one or more electronic elements on a functional substrate and then attaching said functional substrate to said stressed substrate.

16. The method of claim 15 , wherein fabricating said one or more electronic elements comprises forming said one or more electronic elements using a photolithographic semiconductor fabrication process flow.

17. The method of claim 15 , wherein attaching said functional substrate to said stressed substrate comprises using one of a sealing glass and an anodic bond.

18. The method of claim 15 , further comprising forming a plurality of patterned fracture features in said functional substrate.

19. The method of claim 10 , wherein disposing said one or more electronic elements comprises forming said one or more electronic elements directly on the stressed substrate.

20. The method of claim 19 , wherein forming said one or more electronic elements directly on the stressed substrate comprises printing one or more thin film electronic elements on the stressed substrate.

21. A method comprising:
actuating a trigger mechanism attached to a stressed substrate, the stressed substrate including at least one tensile stress layer having a residual tensile stress and at least one compressive stress layer having a residual compressive stress and being operably integrally connected to the at least one tensile stress layer such that the residual tensile and compressive stresses are self-equilibrating; and generating an initial fracture in said stressed substrate in response to actuating the trigger mechanism, wherein the residual tensile and compressive stresses of the stressed substrate are sufficient to generate secondary fractures in response to the initial fracture, the secondary fractures propagating through the stressed substrate.

22. The method of claim 21, further comprising receiving a trigger signal, wherein actuating the trigger mechanism occurs in response to receiving the trigger signal.

23. The method of claim 22, wherein receiving the trigger signal comprises receiving a current pulse or a radio frequency signal.

24. The method of claim 21, wherein generating the initial fracture comprises heating the stressed substrate, initiating a chemical reaction in the stressed substrate, or applying mechanical pressure to the stressed substrate.

25. The method of claim 21, wherein the secondary fractures that propagate through the stressed substrate break a functional layer bonded to the stressed substrate.

Assignees

• Palo Alto Res Ct Inc

Inventors

• Limb Scott J H
• Whiting Gregory L
• Garner Sean R
• Lu Jengping
• De Bruyker Dirk

Classifications

• H10P95/00

  Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass · CPC title

• H10W42/40

  protecting against tampering, e.g. unauthorised inspection or reverse engineering · CPC title

• H10W70/69

  Insulating materials thereof · CPC title

• H10W29/01

  Manufacture or treatment · CPC title

• H10W29/00

  Generic parts of integrated devices, not otherwise provided for · CPC title