Semiconductor devices

Patent metadata

Field	Value
Publication number	US-9997447-B1
Application number	US-201715618083-A
Country	US
Kind code	B1
Filing date	Jun 8, 2017
Priority date	Jun 8, 2017
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

A semiconductor device package includes a carrier, a first insulation layer, a capacitor element, a plurality of interconnection structures, a plurality of substantially parallel top-side metal bars, and a plurality of substantially parallel bottom-side metal bars. The first insulation layer is on the carrier and has a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes. The capacitor element is in the first insulation layer, the capacitor element including a top electrode and a bottom electrode. The plurality of interconnection structures are within the through holes and formed as conductive through holes. The plurality of substantially parallel top-side metal bars are on the first surface of the first insulation layer. The plurality of substantially parallel bottom-side metal bars are on the second surface of the first insulation layer.

First claim

What is claimed is:

1. A semiconductor device package, comprising:
a carrier;
a first insulation layer disposed on the carrier and having a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes;
a second insulation layer disposed on the first surface of the first insulation layer and including portions extending into the first insulation layer;
a capacitor element disposed in the first insulation layer, the capacitor element including a top electrode and a bottom electrode;
a plurality of interconnection structures disposed within the through holes and formed as conductive vias;
a plurality of substantially parallel top-side metal bars disposed on the first surface of the first insulation layer; and
a plurality of substantially parallel bottom-side metal bars disposed on the second surface of the first insulation layer,
wherein each of the conductive vias couples one of the plurality of top-side metal bars to one of the plurality of bottom-side metal bars,
wherein a first one of the plurality of bottom-side metal bars is electrically connected to the top electrode of the capacitor element and a second one of the plurality of bottom-side metal bars is electrically connected to the bottom electrode of the capacitor element, and
wherein the plurality of interconnection structures respectively surround the portions of the second insulation layer extending into the first insulation layer.

2. The semiconductor device package of claim 1 , wherein at least one of the top-side metal bars, at least one of the interconnection structures and at least one of the bottom-side metal bars function as an inductor.

3. The semiconductor device package of claim 1 , wherein a thickness of the interconnection structures is less than about 10 micrometers (μm) and a thickness of at least one of the top-side metal bars and at least one of the bottom-side metal bars is less than about 10 μm.

4. The semiconductor device package of claim 1 , further comprising a third insulation layer disposed between the first insulation layer and the carrier.

5. The semiconductor device package of claim 4 , wherein the first insulation layer includes a first insulation material and the third insulation layer includes a third insulation material different from the first insulation material.

6. The semiconductor device package of claim 1 , wherein the first insulation layer includes a first insulation material and the second insulation layer includes a second insulation material different from the first insulation material.

7. The semiconductor device package of claim 1 , wherein each of the top-side metal bars, the interconnection structures and the bottom-side metal bars comprises a seed layer and a plating layer.

8. The semiconductor device package of claim 7 , wherein a material of the seed layer is different from a material of the plating layer.

9. The semiconductor device package of claim 1 , wherein the carrier includes a glass carrier and a surface roughness of the glass carrier is less than about 1 μm.

10. The semiconductor device package of claim 1 , wherein the interconnection structures function as a shielding element.

11. The semiconductor device package of claim 1 , wherein the first insulation layer is formed from an exposure-type negative photoresist.

12. A semiconductor device package, comprising:
a carrier;
a first insulation layer disposed on the carrier and having a first surface and a second surface adjacent to the carrier and opposite to the first surface, the first insulation layer defining a plurality of through holes, each of the through holes having a first side wall, and the first insulation layer defining a cavity having a second side wall;
a capacitor element in the first insulation layer, the capacitor element including a top electrode and a bottom electrode;
a die disposed in the cavity of the first insulation layer; and
a conductive layer including a plurality of interconnection structures respectively disposed on the first side wall and the second side wall and including a plurality of top continuous portions and a plurality of bottom continuous portions,
wherein the interconnection structures, the top continuous portions and the bottom continuous portions of the conductive layer form an inductor element, and
wherein a first one of the bottom continuous portions of the conductive layer is electrically connected to the top electrode of the capacitor element and a second one of the bottom continuous portions of the conductive layer is electrically connected to the bottom electrode of the capacitor element.

13. The semiconductor device package of claim 12 , wherein a thickness of the interconnection structures is less than about 10 μm.

14. The semiconductor device package of claim 12 , further comprising a second insulation layer disposed between the first insulation layer and the carrier.

15. The semiconductor device package of claim 14 , wherein the first insulation layer includes a first insulation material and the second insulation layer includes a second insulation material different from the first insulation material.

16. The semiconductor device package of claim 12 , wherein the carrier includes a glass carrier and a surface roughness of the glass carrier is less than about 1 μm.

17. The semiconductor device package of claim 12 , wherein the first insulation layer is formed from an exposure-type negative photoresist.

Assignees

• Advanced Semiconductor Eng
• Advanced Ssemiconductor Eng Inc

Inventors

• Chen Chien-Hua
• Lin Hung-Yi
• Hsieh Sheng-Chi

Classifications

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/701

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title