Integrated device package comprising a magnetic core inductor with protective ring embedded in a package substrate

US9496213B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-9496213-B2
Application numberUS-201514836733-A
CountryUS
Kind codeB2
Filing dateAug 26, 2015
Priority dateFeb 5, 2015
Publication dateNov 15, 2016
Grant dateNov 15, 2016

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

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  7. Citations and related patents

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Abstract

Official abstract text for this publication.

An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of interconnects is positioned in the package substrate to at least partially surround the magnetic core. At least one interconnect from the second plurality of interconnects is also part of the first plurality of interconnects. In some implementations, the first protective ring is a non-contiguous protective ring. In some implementations, the first inductor is a solenoid inductor. In some implementations, the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer.

First claim

Opening claim text (preview).

What is claimed is: 1. An integrated device package comprising: a die; and a package substrate coupled to the die, the package substrate comprising: at least one dielectric layer; a magnetic core in the at least one dielectric layer; a first protective ring; and a first inductor comprising a plurality of first interconnects, the first inductor positioned in the package substrate to at least partially surround the magnetic core, wherein the first protective ring comprises at least one interconnect from the plurality of first interconnects of the first inductor. 2. The integrated device package of claim 1 , wherein the first protective ring comprises a non-contiguous protective ring. 3. The integrated device package of claim 1 , wherein the first protective ring comprises a contiguous protective ring. 4. The integrated device package of claim 1 , wherein the package substrate further comprises a second protective ring comprising at least one second interconnect from the plurality of first interconnects of the first inductor. 5. The integrated device package of claim 4 , wherein the first protective ring is located on a first metal layer of the package substrate and the second protective ring is located on a second metal layer of the package substrate. 6. The integrated device package of claim 4 , wherein the first protective ring comprises a first contiguous protective ring or a first non-contiguous protective ring, and the second protective ring comprises a second contiguous protective ring or a second non-contiguous protective ring. 7. The integrated device package of claim 1 , wherein the package substrate further comprises a second inductor comprising a plurality of second interconnects. 8. The integrated device package of claim 7 , wherein the first inductor and the second inductor are configured to operate as a coupled inductor. 9. The integrated device package of claim 7 , wherein the first inductor and the second inductor are configured to operate as a transformer. 10. The integrated device package of claim 7 , wherein the second inductor is positioned in the package substrate to at least partially surround the magnetic core, wherein the first protective ring comprises at least one interconnect from the plurality of second interconnects of the second inductor. 11. The integrated device package of claim 1 , wherein the at least one interconnect from the plurality of first interconnects that is part of the first protective ring, is configured to reduce eddy currents and provide improved shielding for the first inductor. 12. The integrated device package of claim 1 , wherein the first inductor comprises a solenoid inductor. 13. The integrated device package of claim 1 , wherein the first protective ring at least partially surrounds the magnetic core. 14. The integrated device package of claim 1 , wherein a spacing between the magnetic core and the first inductor is about 50 microns (μm) or less. 15. The integrated device package of claim 1 , wherein a spacing between the magnetic core and the first protective ring is about 50 microns (μm) or less. 16. The integrated device package of claim 1 , wherein the magnetic core includes a carrier, a first magnetic layer, and a second magnetic layer. 17. The integrated device package of claim 1 , wherein the plurality of first interconnects comprises a trace, a via, and/or a pad. 18. The integrated device package of claim 1 , wherein the integrated device package is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a navigation device, a communications device, a mobile device, a mobile phone, a smartphone, a personal digital assistant, a fixed location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, and a device in a automotive vehicle, and further including the device. 19. A method for fabricating an integrated device package, comprising: forming a package substrate, wherein forming the package substrate comprises: forming at least one dielectric layer; providing a magnetic core in the at least one dielectric layer; forming a first metal layer to define a first protective ring in the package substrate; and forming a plurality of first interconnects to define a first inductor in the package substrate, wherein forming the plurality of first interconnects comprises: forming the plurality of first interconnects in the package substrate such that the plurality of first interconnects at least partially surrounds the magnetic core, and using at least a portion of the first metal layer, to form an interconnect from the plurality of first interconnects, to define the first inductor; and coupling the package substrate to a die. 20. The method of claim 19 , wherein forming the first metal layer to define the first protective ring in the package substrate comprises forming the first metal layer to define a non-contiguous protective ring in the package substrate. 21. The method of claim 19 , wherein forming the first metal layer to define the first protective ring in the package substrate comprises forming the first metal layer to define a contiguous protective ring in the package substrate. 22. The method of claim 19 , wherein forming the package substrate further comprises forming a second metal layer to define a second protective ring in the package substrate such that the second protective ring comprises at least one second interconnect from the plurality of first interconnects. 23. The method of claim 22 , wherein forming the first metal layer to define the first protective ring comprises forming a plurality of second interconnects, and wherein forming the second metal layer to define the second protective ring comprises forming a plurality of third interconnects. 24. The method of claim 19 , wherein forming a package substrate further comprises forming a plurality of second interconnects to define a second inductor in the package substrate, wherein forming the plurality of second interconnects comprises: forming the plurality of second interconnects in the package substrate such that the plurality of second interconnects at least partially surround the magnetic core; and using at least a second portion of the first metal layer to form at least one interconnect from the plurality of second interconnects, to define the second inductor. 25. The method of claim 19 , wherein the first inductor comprises a solenoid inductor. 26. The method of claim 19 , wherein forming the at least one dielectric layer comprises: forming a first dielectric layer, wherein the first dielectric layer is a core layer; and forming a second dielectric layer. 27. The method of claim 19 , wherein a spacing between the magnetic core and the first inductor is about 50 microns (μm) or less. 28. The method of claim 19 , wherein a spacing between the magnetic core and the first protective ring is about 50 microns (μm) or less. 29. The method of claim 19 , wherein providing the magnetic core in the dielectric layer comprises providing a carrier, a first magnetic layer, and a second magnetic layer. 30. The method of claim 19 , wherein the integrated device package is incorporated into a device selected from a group consisting of a music player, a video player, an entertainment unit, a na

Assignees

Inventors

Classifications

  • between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

  • Interconnections or connectors in packages · CPC title

  • H10W70/685Primary

    comprising multiple insulating layers · CPC title

  • of insulating or insulated package substrates, or of interposers, or of redistribution layers (manufacture or treatment of leadframes H10W70/04) · CPC title

  • Arrangements for protection of devices (arrangements for thermal protection H10W40/00) · CPC title

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Frequently asked questions

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What does patent US9496213B2 cover?
An integrated device package includes a die and a package substrate. The package substrate includes at least one dielectric layer (e.g., core layer, prepeg layer), a magnetic core in the dielectric layer, a first plurality of interconnects configured to operate as a first protective ring, and a second plurality of interconnects configured to operate as a first inductor. The second plurality of …
Who is the assignee on this patent?
Qualcomm Inc
What technology area does this patent fall under?
Primary CPC classification H10W70/685. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Nov 15 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 1 related publication on this page (citations in our corpus or others sharing the same primary CPC).