Interdigitated capacitor to integrate with flash memory

Patent metadata

Field	Value
Publication number	US-9590059-B2
Application number	US-201514851284-A
Country	US
Kind code	B2
Filing date	Sep 11, 2015
Priority date	Dec 24, 2014
Publication date	Mar 7, 2017
Grant date	Mar 7, 2017

Abstract

Some embodiments relate to an integrated circuit (IC). The IC includes a semiconductor substrate including a flash memory region and a capacitor region. A flash memory cell is arranged over the flash memory region and includes a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell. The flash memory cell also includes a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer. A capacitor is arranged over the capacitor region and includes: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and separated from one another by a capacitor dielectric layer. The capacitor dielectric layer and control gate dielectric layer are made of the same material.

First claim

What is claimed is:

1. An integrated circuit (IC), comprising:
a semiconductor substrate including a flash memory region and a capacitor region;
a flash memory cell arranged over the flash memory region and including: a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell, and a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer; and
a capacitor arranged over the capacitor region and including: a polysilicon first capacitor plate and polysilicon second capacitor plate, which are inter-digitated with one another and have sidewalls separated from one another by a capacitor dielectric layer, wherein the capacitor dielectric layer and control gate dielectric layer are made of the same material; and
wherein uppermost surfaces of the select gate and first capacitor plate are co-planar with one another.

2. The IC of claim 1 , wherein the capacitor dielectric layer and control gate dielectric layer each comprise a charge trapping layer sandwiched between first and second dielectric layers.

3. The IC of claim 1 , wherein the capacitor dielectric layer and control gate dielectric layer each comprise a tunnel dielectric layer, a capping dielectric layer, and a layer of silicon dots sandwiched between the tunnel dielectric layer and the capping dielectric layer.

4. The IC of claim 1 , wherein the capacitor dielectric layer and control gate dielectric layer each comprise a tunnel oxide layer, a capping oxide layer, and a nitride layer sandwiched between the tunnel oxide layer and the capping dielectric layer.

5. The IC of claim 1 , wherein the first capacitor plate has an upper surface and a thickness corresponding to those of the select gate; and wherein the second capacitor plate has an upper surface and thickness corresponding to those of the control gate.

6. The IC of claim 1 , wherein upper outermost surfaces of the control gate and capacitor plate are rounded.

7. The IC of claim 1 , wherein polysilicon material of the first capacitor plate is formed concurrently with polysilicon material of the select gate; and wherein polysilicon material of the second capacitor plate is formed concurrently with polysilicon material of the control gate.

8. The IC of claim 1 , further comprising:
a doped capacitor region arranged in the capacitor region of the semiconductor substrate;
wherein the doped capacitor region is ohmically coupled to one of the first capacitor plate or the second capacitor plate such that the doped capacitor region and the one of the first capacitor plate or the second capacitor plate collectively act as a single capacitor plate.

9. The IC of claim 1 , wherein the first capacitor plate includes a first plurality of fingers that extend outward from a first trunk which extends continuously between the first plurality of fingers.

10. The IC of claim 9 , wherein the second capacitor plate includes a second plurality of fingers that extend outward from a second trunk which extends continuously between the second plurality of fingers, and wherein the first plurality of fingers are inter-digitated with the second plurality of fingers and are separated there from by the capacitor dielectric layer.

11. A method for manufacturing an embedded flash memory device, the method comprising:
receiving a semiconductor substrate, which includes a flash region and a capacitor region;
forming a first dielectric layer over the flash and capacitor regions of the semiconductor substrate, and forming a first doped polysilicon layer over the first dielectric layer; and
removing some portions of the first polysilicon layer and first dielectric layer to establish a select gate over the flash region and a first capacitor plate over the capacitor region, wherein uppermost surfaces of the select gate and the first capacitor plate are co-planar with one another.

12. The method of claim 11 , further comprising:
forming a second dielectric layer which is conformal along sidewalls and upper surfaces of the select gate and the first capacitor plate;
forming a second doped polysilicon layer which is conformal along sidewalls and upper surfaces of the second dielectric layer; and
removing some portions of the second polysilicon layer and second dielectric layer to concurrently establish a control gate alongside the select gate and a second capacitor plate alongside the first capacitor plate.

13. The method of claim 12 , wherein the first capacitor plate includes a first plurality of fingers that extend outward from a first trunk which extends continuously between the first plurality of fingers.

14. The method of claim 13 , wherein the second capacitor plate includes a second plurality of fingers that extend outward from a second trunk which extends continuously between the second plurality of fingers.

15. The method of claim 14 , wherein the first plurality of fingers are inter-digitated with the second plurality of fingers and the second dielectric layer resides between neighboring sidewalls of the first and second plurality of fingers to separate the first and second plurality of fingers from one another.

16. An integrated circuit (IC), comprising:
a semiconductor substrate including a flash memory region and a capacitor region;
a flash memory cell arranged over the flash memory region and including: a polysilicon select gate arranged between first and second source/drain regions of the flash memory cell, and a control gate arranged alongside the select gate and separated from the select gate by a control gate dielectric layer; and
a capacitor arranged over the capacitor region and including: a polysilicon first capacitor plate, a capacitor dielectric layer that conformally and laterally surrounds the polysilicon first capacitor plate, and a polysilicon second capacitor plate that conformally and laterally surrounds the capacitor dielectric layer, wherein at least one of the first and second capacitor plates includes one or more fingers that extend into one or more corresponding sidewall recesses in the other of the first and second capacitor plates such that the first and second capacitor plates are inter-digitated with one another and separated from one another by the capacitor dielectric layer; and
wherein uppermost surfaces of the select gate and first capacitor plate are co-planar with one another.

17. The IC of claim 16 , wherein the capacitor dielectric layer and control gate dielectric layer are made of the same material.

18. The IC of claim 16 , wherein the capacitor dielectric layer and control gate dielectric layer each comprise a tunnel dielectric layer, a capping dielectric layer, and a layer of silicon dots sandwiched between the tunnel dielectric layer and the capping dielectric layer.

19. The IC of claim 16 , wherein the capacitor dielectric layer and control gate dielectric layer each comprise a tunnel oxide layer, a capping oxide layer, and a nitride layer sandwiched between the tunnel oxide layer and the capping dielectric layer.

20. The IC of claim 16 , wherein the first capacitor plate has an upper surface and a thickness corresponding to those of the select gate; and wherein the second capacitor plate has an upper surface and thickness corresponding to those of the control gate.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chuang Harry-Hak-Lay
• Wang Yu-Hsiung
• Liu Chen-Chin

Classifications

• H10D84/813

  Combinations of field-effect devices and capacitor only · CPC title

• H01L29/42344 Primary

  Electricity · mapped topic

• H01L27/0629

  Electricity · mapped topic

• H01L28/90

  Electricity · mapped topic

• H01L27/11573

  Electricity · mapped topic