Three dimensional memory device including memory cells with resistance change layers

Patent metadata

Field	Value
Publication number	US-9508430-B2
Application number	US-201514849023-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Mar 10, 2015
Publication date	Nov 29, 2016
Grant date	Nov 29, 2016

Abstract

A memory device includes a plurality of first interconnects extending in a first direction; a plurality of second interconnects extending in the first direction; a plurality of third interconnects extending in a third direction; and memory cells each with resistance change layers provided on two side surfaces of a corresponding one of the third interconnects, which surfaces are opposite to each other in the second direction. The resistance change layers are connected to the different second interconnects. A plurality of selectors connect the third interconnects to the first interconnects. One of the selectors includes a semiconductor layer provided between the corresponding third interconnect and the corresponding first interconnect. Gates extending in the second direction and provided, via a gate insulating film, on two side surfaces that are opposite to each other in the first direction.

First claim

What is claimed is:

1. A memory device comprising:
a plurality of first interconnects extending in a first direction, and provided in a second direction that is different from the first direction;
a plurality of second interconnects extending in the first direction, and provided in the second direction and a third direction that is different from the first direction and the second direction;
a plurality of third interconnects extending in the third direction, and provided in the first direction and second direction;
memory cells each with resistance change layers provided on two side surfaces of a corresponding one of the third interconnects which surfaces are opposite to each other in the second direction, the resistance change layers being connected to the different second interconnects; and
a plurality of selectors connecting the third interconnects to the first interconnects,
wherein one of the selectors includes a semiconductor layer provided between the corresponding third interconnect and the corresponding first interconnect, and
gates extending in the second direction and provided, via a gate insulating film, on two side surfaces that are opposite to each other in the first direction.

2. The device according to claim 1 , wherein the selector shares one of the gates with another selector adjacent to the selector.

3. The device according to claim 2 , wherein one of the selectors corresponding to one of the third interconnects to which the memory cell from which data is to be read is connected, a select voltage is applied to one of the gates provided on the two side surfaces, and an unselect voltage is applied to another of the gates,
every other interconnect of the second interconnects belongs to an identical interconnect group, and
an identical voltage is applied to two or more of the second interconnects which belong to the identical interconnect group during operation.

4. The device according to claim 1 ,
further comprising:
a fourth interconnect extending in the second direction; and
a fifth interconnect extending in the second direction,
wherein
the plurality of second interconnects include a sixth interconnect connected to the fourth interconnect and a seventh interconnect which is adjacent to the sixth interconnect in the second direction and which is connected to the fifth interconnect.

5. The device according to claim 1 ,
further comprising:
a fourth interconnect extending in the second direction;
a fifth interconnect extending in the second direction;
a sixth interconnect extending in the second direction;
a first memory area including the plurality of second interconnects; and
a second memory area including the plurality of second interconnects and which is adjacent to the first memory area in the first direction,
wherein
the plurality of second interconnects include a seventh interconnect and an eighth interconnect adjacent to the seventh interconnect in the second direction,
in the first memory area,
the seventh interconnect is connected to the fourth interconnect, and
the eighth interconnect is connected to the fifth interconnect, and
in the second memory area,
the seventh interconnect is connected to the sixth interconnect, and
the eighth interconnect is connected to the fourth interconnect.

6. The device according to claim 5 ,
wherein
the fourth interconnect extending in the second direction is provided at a boundary between the first memory area and the second memory area.

7. The device according to claim 1 ,
further comprising:
a fourth interconnect extending in the second direction;
a fifth interconnect extending in the second direction;
a sixth interconnect extending in the second direction;
a first memory area including the plurality of second interconnects; and
a second memory area including the plurality of second interconnects and which is adjacent to the first memory area in the first direction,
wherein
the plurality of second interconnects include a seventh interconnect and an eighth interconnect adjacent to the seventh interconnect in the second direction,
in the first memory area,
the seventh interconnect is connected to the fourth interconnect, and
the eighth interconnect is connected to the fifth interconnect, and
in the second memory area,
the seventh interconnect is connected to the fourth interconnect, and
the eighth interconnect is connected to the sixth interconnect.

8. The device according to claim 7 ,
wherein
the fourth interconnect extending in the second direction is provided at a boundary between the first memory area and the second memory area.

9. A memory device comprising:
a plurality of first interconnects extending in a first direction, and provided in a second direction that is different from the first direction;
a plurality of second interconnects extending in the first direction and the second direction, and provided in a third direction that is different from the first direction and the second direction;
a plurality of third interconnects extending in the third direction, and provided in the first direction and second direction;
memory cells each with a resistance change layer provided on a side surface of a corresponding one of the third interconnects which surface extends along the third direction, the resistance change layer being connected to the second interconnect; and
a plurality of selectors connecting the third interconnects to the first interconnects,
wherein one of the selectors includes a semiconductor layer provided between the corresponding third interconnect and the corresponding first interconnect, and
gates extending in the second direction and provided, via a gate insulating film, on two side surfaces that are opposite to each other in the first direction.

10. The device according to claim 1 ,
wherein
the first direction and the second direction are orthogonal to each other.

11. The device according to claim 1 ,
wherein
the first direction and the third direction are orthogonal to each other.

12. The device according to claim 1 ,
wherein
the second direction and the third direction are orthogonal to each other.

13. The device according to claim 1 ,
wherein
the first direction and the second direction are orthogonal to each other,
the first direction and the third direction are orthogonal to each other, and
the second direction and the third direction are orthogonal to each other.

14. The device according to claim 6 ,
further comprising
an area which connects the fourth interconnect, the fifth interconnect, and the sixth interconnect to a base transistor and which is adjacent to the first memory area and the second memory area in the second direction.

15. The device according to claim 8 ,
further comprising
an area which connects the fourth interconnect, the fifth interconnect, and the sixth interconnect to a peripheral circuit and which is adjacent to the first memory area and the second memory area in the second direction.

16. A memory device comprising:
a plurality of first interconnects each extending in a first direction, and provided in a second direction that is different from the first direction;
a plurality of second interconnects each extending in the first direction, and provided in the second direction and a third direction that is different from the first direction and the second direction;
a plurality of third interconnects each extending in the third direction, and provided in the first direction and second direction;
memory cells each with resistance change layers provided on two side surf

Assignees

• Toshiba Kk

Inventors

• Murooka Kenichi

Classifications

• G11C13/0026

  Bit-line or column circuits · CPC title

• G11C13/0097

  Erasing, e.g. resetting, circuits or methods · CPC title

• G11C13/0069

  Writing or programming circuits or methods · CPC title

• G11C2213/77

  Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used · CPC title

• G11C13/0023

  Address circuits or decoders · CPC title