Devices, systems, and methods of reducing chip select

Patent metadata

Field	Value
Publication number	US-9996496-B2
Application number	US-201715685855-A
Country	US
Kind code	B2
Filing date	Aug 24, 2017
Priority date	Aug 7, 2013
Publication date	Jun 12, 2018
Grant date	Jun 12, 2018

Abstract

Several systems and methods of chip select are described. In one such method, a device maintains two identifiers, (ID_a and ID_m). When the device receives a command, it examines the values of ID_a and ID_m relative to a third reference identifier (ID_s). If either ID_a or ID_m is equivalent to ID_s, the device executes the command, otherwise, the device ignores the command. By using two different identification methods, a system has options in choosing to activate devices, being able to selectively switch between selecting multiple devices and single devices in a quick manner. In another such method, a device may have a persistent area that stores identification information such as an ID_a. Thus, system functionality may remain independent from any defect/marginality associated with the physical or logical components required for initial ID_a assignment of all devices in the system.

First claim

What is claimed is:

1. A memory device comprising:
a chip select input;
a command/address input to receive signals associated with execution of an operation by the memory device, when the memory device is identified as accessible, in conjunction with a chip select signal received at the chip select input; and
a persistent area, the persistent area configured to contain assigned identifiers of the memory device such that the memory device is accessible in response to reception of a select identification signal having a select identifier matching one of the assigned identifiers.

2. The memory device of claim 1 , wherein the memory device is configured with one of the assigned identifiers being a master identifier such that the master identifier overrides the other assigned identifiers of the assigned identifiers in operatively responding to a received command signal.

3. The memory device of claim 1 , wherein the memory device is configured to execute subsequent received commands after reception of the select identification signal having the select identifier matching one of the assigned identifiers until reception of a select identification signal having a select identifier that does not match one of the assigned identifiers of the memory device.

4. The memory device of claim 1 , wherein the memory device includes a select input and a select output to conduct an assignment sequence with respect to assigning identifiers to the memory device and the memory device is operable to adjust levels at the select input and the select output to set an assigned identifier for another memory device when coupled with the other memory device in a daisy chain.

5. The memory device of claim 1 , wherein the memory device is operable to receive the assigned identifiers via the command/address input.

6. The memory device of claim 1 , wherein the persistent area is an area of poly-fuses or an area of metal fuses.

7. The memory device of claim 1 , wherein the persistent area is an area of memory array cells or non-volatile memory in the memory device.

8. The memory device of claim 1 , wherein the memory device is configured to maintain an individual assigned identifier of the assigned identifiers once set until changed in a power cycle and/or an identification reassignment sequence.

9. A system comprising:
memory devices coupled together in a daisy chain, each memory device including:
a chip select input;
a command/address input to receive signals associated with execution of an operation by the respective memory device, when the respective memory device is identified as accessible, in conjunction with a chip select signal received at the chip select input; and
a persistent area, the persistent area configured to contain assigned identifiers of the respective memory device such that the respective memory device is accessible in response to reception of a select identification signal having a select identifier matching one of the assigned identifiers;

a chip select line coupled to the chip select input of each memory device; and
a command/address line coupled to the command/address input of each memory device.

10. The system of claim 9 , wherein each memory device is configured with one of the assigned identifiers being a master identifier such that the master identifier overrides the other assigned identifiers of the assigned identifiers in operatively responding to a received command signal in the respective memory device.

11. The system of claim 9 , wherein the system is operable to assign identifiers to the memory devices in the daisy chain to operatively provide individual operation of the memory devices or parallel operation of selected memory devices.

12. The system of claim 11 , wherein the selected memory devices for selected parallel operation have an identical assigned identifier selected in the selected memory devices.

13. The system of claim 9 , wherein the persistent area is an area of poly-fuses or an area of metal fuses.

14. The system of claim 9 , wherein each memory device has a select input and a select output, the memory devices arranged in the daisy chain with the select output of one memory device coupled to the select input of a next memory device in the daisy chain.

15. The system of claim 14 , wherein each memory device is operable to adjust levels at its select input and its select output to set an assigned identifier for the next memory device in the daisy chain.

16. A method comprising:
receiving a command at memory devices coupled in a daisy chain, each memory device including:
a chip select input coupled to a chip select line;
a command/address input coupled to a command/address line to receive signals associated with execution of an operation by the respective memory device, when the respective memory device is identified as accessible, in conjunction with a chip select signal received at the chip select input; and
a persistent area, the persistent area configured to contain assigned identifiers of the respective memory device such that the respective memory device is accessible in response to reception of a select identification signal having a select identifier matching one of the assigned identifiers;

determining, for each memory device in the daisy chain, if the command is intended for the respective memory device based on a comparison a select identifier associated with the command with assigned identifiers of the respective memory device; and
performing the command when the command is intended for the respective memory device.

17. The method of claim 16 , wherein the comparison includes comparing the select identifier associated with the command to a master identifier of the assigned identifiers.

18. The method of claim 17 , wherein comparing the select identifier associated with the command to a master identifier of the assigned identifiers includes, upon determination that the select identifier associated with the command equals the master identifier, refraining from comparing the select identifier associated with the command to other assigned identifiers of the respective memory device.

19. The method of claim 16 , wherein the method includes assigning an assigned identifier to one or more of the memory devices while situated in the daisy chain.

20. The method of claim 19 , wherein the method includes memory devices in the daisy chain not having an assigned identifier assigned while situated in the daisy chain using assigned identifiers stored in their respective persistent area while in a manufacturing environment.

21. The method of claim 16 , wherein the method includes isolating one or more spare memory devices in the daisy chain from operating based on generating signals correlated to not select an assigned identifier of the one or more spare memory devices.

Assignees

• Micron Technology Inc

Inventors

• Rivers Doyle
• Ruby Paul D
• Ramalingam Anand S
• Sundaram Rajesh
• Walker Julie M

Classifications

• G06F13/385

  for adaptation of a particular data processing system to different peripheral devices · CPC title

• G06F13/14

  Handling requests for interconnection or transfer · CPC title

• G06F13/4247 Primary

  on a daisy chain bus · CPC title