Systems and methods for fabrication of superconducting integrated circuits

Patent metadata

Field	Value
Publication number	US-9978809-B2
Application number	US-201615289782-A
Country	US
Kind code	B2
Filing date	Oct 10, 2016
Priority date	Feb 27, 2009
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

Various techniques and apparatus permit fabrication of superconductive circuits and structures, for instance Josephson junctions, which may, for example be useful in quantum computers. For instance, a low magnetic flux noise trilayer structure may be fabricated having a dielectric structure or layer interposed between two elements or layers capable of superconducting. A superconducting via may directly overlie a Josephson junction. A structure, for instance a Josephson junction, may be carried on a planarized dielectric layer. A fin may be employed to remove heat from the structure. A via capable of superconducting may have a width that is less than about 1 micrometer. The structure may be coupled to a resistor, for example by vias and/or a strap connector.

First claim

We claim:

1. A superconducting circuit comprising:
a Josephson junction having a first electrode formed of a first material that superconducts at or below a first critical temperature, a second electrode formed of the first material that superconducts at or below the first critical temperature and an electrically insulative layer interposed between the first and the second electrodes to separate the first electrode from the second electrode;
a first superconducting current path comprised of a second material that superconducts at or below a second critical temperature, wherein the second material has a magnetic flux noise coefficient less than about 1.0 and the first superconducting current path is coupled to the first electrode; and
a second superconducting current path comprised of a third material that superconducts at or below a third critical temperature, wherein the material has a magnetic flux noise coefficient less than about 1.0 and the second superconducting current path is coupled to the second electrode, wherein the first material is different from the second and the third material.

2. The superconducting circuit of claim 1 wherein the second material comprises at least one material selected from the group consisting of: zinc, tin, and lead.

3. The superconducting circuit of claim 2 wherein the third material of which the second superconducting current path is comprised is the same material as the second material.

4. The superconducting circuit of claim 1 , further comprising:
a substrate which carries the Josephson junction, the first superconducting current path, and the second superconducting current path, wherein the substrate comprises at least one material selected from the group consisting of: silicon, and sapphire.

5. The superconducting circuit of claim 1 wherein the first and the second superconducting current paths are galvanically coupled together to form a closed superconducting loop interrupted by the Josephson junction.

6. The superconducting circuit of claim 1 wherein the first and the second electrodes are comprised of niobium and the electrically insulative layer is comprised of at least a layer of aluminum oxide.

7. An integrated circuit comprising:
a substrate;
a metal layer deposited on the substrate, wherein the metal layer includes at least one electrical current path that superconducts at or below a critical temperature;
a first dielectric layer deposited on the metal layer wherein at least a portion of the first dielectric layer is planarized;
a first trilayer Josephson junction deposited on the first dielectric layer wherein the first trilayer Josephson junction is comprised of a first electrode, a second electrode, and an electrically insulative layer interposed between the first and the second electrodes, and wherein the first and the second electrodes are each formed of a material that superconducts at or below a critical temperature;
a second dielectric layer deposited on the first trilayer Josephson junction;
a second metal layer deposited on the second dielectric layer, wherein the second metal layer includes at least one electrical current path that superconducts at or below a critical temperature, and
a superconducting via that superconductingly electrically couples at least one electrical current path from the second metal layer with the first electrode of the first trilayer Josephson junction, wherein the superconducting via comprises a hole extending through the second dielectric layer that is at least partially filled with a material that is superconducting at or below a critical temperature.

8. The integrated circuit of claim 7 wherein the at least one electrical current path is comprised of at least one material selected from the group consisting of: niobium, aluminum, zinc, tin, and lead.

9. The integrated circuit of claim 7 , further comprising: a resistor, wherein the resistor is carried by the first dielectric layer and the resistor is thermally conductively coupled to the substrate.

10. The integrated circuit of claim 7 , further comprising:
a resistor carried by the substrate; and
a second trilayer Josephson junction that is carried by the substrate wherein the second trilayer Josephson junction comprises a third electrode that superconducts at or below a critical temperature, a fourth electrode that superconducts at or below a critical temperature, and a second electrically insulative layer interposed between the third and the fourth electrodes and wherein the third electrode of the second trilayer Josephson junction is electrically coupled to the resistor.

11. An integrated circuit, comprising:
a substrate;
a metal layer deposited on the substrate, wherein the metal layer includes at least one electrical current path that superconducts at or below a critical temperature;
a first dielectric layer deposited on the metal layer wherein at least a portion of the first dielectric layer is planarized;
a first trilayer Josephson junction deposited on the first dielectric layer wherein the first trilayer Josephson junction is comprised of a first electrode, a second electrode, and an electrically insulative layer interposed between the first and the second electrodes, and wherein the first and the second electrodes are each formed of a material that superconducts at or below a critical temperature;
a second dielectric layer deposited on the first trilayer Josephson junction;
a second metal layer deposited on the second dielectric layer, wherein the second metal layer includes at least one electrical current path that superconducts at or below a critical temperature, and
a superconducting via that superconductingly electrically couples at least one electrical current path from the second metal layer with at least one electrical current path from the first metal layer, wherein the superconducting via comprises a hole extending through both the first and the second dielectric layers, and wherein the hole is at least partially filled with a material that is superconducting at or below a critical temperature.

12. An integrated circuit, comprising:
a substrate;
a metal layer deposited on the substrate, wherein the metal layer includes at least one electrical current path that superconducts at or below a critical temperature;
a first dielectric layer deposited on the metal layer wherein at least a portion of the first dielectric layer is planarized;
a first trilayer Josephson junction deposited on the first dielectric layer wherein the first trilayer Josephson junction is comprised of a first electrode, a second electrode, and an electrically insulative layer interposed between the first and the second electrodes, and wherein the first and the second electrodes are each formed of a material that superconducts at or below a critical temperature;
a resistor carried by the substrate;
a second trilayer Josephson junction that is carried by the substrate wherein the second trilayer Josephson junction comprises a third electrode that superconducts at or below a critical temperature, a fourth electrode that superconducts at or below a critical temperature, and a second electrically insulative layer interposed between the third and the fourth electrodes and wherein the third electrode of the second trilayer Josephson junction is electrically coupled to the resistor;
a dielectric layer carried by the substrate wherein the dielectric layer is deposited on at least a portion of the resistor;
a first via formed through the dielectric layer wherein the first electrode of the first trilayer Josephson junction is electrically coupled to the resistor through the first via; and
a second via formed through the dielectri

Assignees

• D Wave Systems Inc

Inventors

• Ladizinsky Eric
• Rose Geordie
• Hilton Jeremy P
• Dantsker Eugene
• Oh Byong Hyop

Classifications

• B82Y10/00 Primary

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• Y10S977/943

  Information storage or retrieval using nanostructure · CPC title

• Y10S977/723

  On an electrically insulating substrate · CPC title

• Y10S977/707

  having different types of nanoscale structures or devices on a common substrate · CPC title

• H01L39/223

  Electricity · mapped topic