Stack type semiconductor package
US-9230876-B2 · Jan 5, 2016 · US
Packaged semiconductor chips having heat dissipation layers and ground contacts therein
US9978661B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-9978661-B2 |
| Application number | US-201615235958-A |
| Country | US |
| Kind code | B2 |
| Filing date | Aug 12, 2016 |
| Priority date | Aug 13, 2015 |
| Publication date | May 22, 2018 |
| Grant date | May 22, 2018 |
How to read this patent
A practical reading order for non-experts. Skip the full description unless you need deep technical detail.
- Title
What the patent document calls the invention.
- Abstract
A short plain-language summary of the technical disclosure.
- Assignees and inventors
Who owns or filed the patent and who is credited as inventor.
- Key dates
Filing, priority, publication, and grant dates set the timeline.
- First independent claim
The legal scope of protection — read this for what is actually claimed.
- CPC / IPC classifications
Technology tags used to group this patent with similar filings.
- Citations and related patents
Prior art links and similar publications in this corpus.
Abstract
Official abstract text for this publication.
Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat dissipation layer provided on the top surface of the semiconductor chip. The mold layer may have a top surface substantially coplanar with the top surface of the semiconductor chip, and the top surfaces of the semiconductor chip and the mold layer may have a difference in surface roughness from each other.
First claim
Opening claim text (preview).
What is claimed is: 1. A semiconductor package, comprising: a package substrate comprising a top surface and a bottom surface facing each other and a ground pad on the top surface of the package substrate; a semiconductor chip mounted on the top surface of the package substrate, the semiconductor chip comprising a bottom surface facing the top surface of the package substrate and a top surface that is opposite the bottom surface thereof; a mold layer lying on the top surface of the package substrate to enclose the semiconductor chip and having a top surface that is coplanar with the top surface of the semiconductor chip; and a heat dissipation layer provided on the semiconductor chip and the mold layer, wherein the heat dissipation layer is in direct contact with the top surface of the semiconductor chip and the top surface of the mold layer and comprises a ground contact that passes through the mold layer and is electrically connected to the ground pad, and the top surface of the semiconductor chip has a surface roughness that is smaller than a surface roughness of the top surface of the mold layer. 2. The semiconductor package of claim 1 , wherein the heat dissipation layer comprises: a bottom surface that is in direct contact with the top surface of the semiconductor chip and the top surface of the mold layer; and a top surface that is opposite the bottom surface thereof, wherein the top surface of the heat dissipation layer is uneven. 3. The semiconductor package of claim 1 , wherein the heat dissipation layer has a uniform thickness on the top surface of the package substrate. 4. The semiconductor package of claim 1 , wherein the heat dissipation layer has a non-uniform thickness on the top surface of the package substrate. 5. The semiconductor package of claim 1 , wherein the heat dissipation layer completely covers the top surfaces of the semiconductor chip and the mold layer. 6. The semiconductor package of claim 1 , wherein the heat dissipation layer covers a portion of the top surface of the semiconductor chip and a portion of the top surface of the mold layer.
Assignees
Inventors
Classifications
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between a chip and a stacked insulating package substrate, interposer or RDL · CPC title
between stacked chips · CPC title
characterised by the relative positions of pads or connectors relative to package parts · CPC title
Patent family
Related publications grouped by family.
External sources
Frequently asked questions
Answers are generated from the same data shown on this page.
- What does patent US9978661B2 cover?
- Semiconductor packages and methods of fabricating the same are disclosed. The semiconductor package may include a package substrate, a semiconductor chip, which is mounted on the package substrate to have a bottom surface facing the package substrate and a top surface opposite to the bottom surface, a mold layer provided on the package substrate to encapsulate the semiconductor chip, and a heat…
- Who is the assignee on this patent?
- Im Yunhyeok, Feygenson Oleg, Kim Sang Il, and 5 more
- What technology area does this patent fall under?
- Primary CPC classification H10W40/22. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue May 22 2018 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 5 related publications on this page (citations in our corpus or others sharing the same primary CPC).