Stack type semiconductor package

Patent metadata

Field	Value
Publication number	US-9230876-B2
Application number	US-201414267259-A
Country	US
Kind code	B2
Filing date	May 1, 2014
Priority date	Jun 19, 2013
Publication date	Jan 5, 2016
Grant date	Jan 5, 2016

Abstract

A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.

First claim

What is claimed is:

1. A stack type semiconductor package comprising:
a lower semiconductor package comprising a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and comprises a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface;
an upper semiconductor package comprising an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate;
an inter-package connection unit which connects the lower package substrate and the upper package substrate;
a heat dissipation member which is formed on the second surface of the lower semiconductor chip;
an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate;
a plurality of first upper lands which are formed on a top surface of the upper package substrate to be insulated from one another by a first solder resist layer, and which the upper semiconductor chip is connected;
a plurality of second upper lands and a plurality of third upper lands which are formed on the bottom surface of the upper package substrate, the second upper lands are insulated from the third upper lands by a second solder resist layer, and which the inter-package connection unit and the interconnection unit are respectively connected,
wherein a maximum height of the inter-package connection unit measured in a first direction is substantially greater than a maximum height of the interconnection unit measured in the first direction, wherein the first direction is perpendicular to the top surface of the lower package substrate, and
wherein the third upper lands are not electrically connected to the first upper lands and the second upper lands, and the second upper lands and the third upper lands have different exposure sizes.

2. The stack type semiconductor package of claim 1 , wherein the interconnection unit comprises a solder ball.

3. The stack type semiconductor package of claim 1 , wherein the interconnection unit is formed on a portion of the bottom surface of the upper package substrate corresponding to the lower semiconductor chip.

4. The stack type semiconductor package of claim 1 , wherein the heat dissipation member comprises a metal layer fully plated on the second surface of the lower semiconductor chip.

5. The stack type semiconductor package of claim 1 , wherein the interconnection unit comprises a plurality of solder balls, and
the heat dissipation member comprises a plurality of metal patterns which are formed using an inkjet printing method,
wherein the plurality of metal patterns are formed to respectively correspond to the plurality of solder balls.

6. The stack type semiconductor package of claim 1 , further comprising a lower molding material which is formed on the lower package substrate and surrounds a side surface of the lower semiconductor chip.

7. The stack type semiconductor package of claim 6 , wherein the heat dissipation member is formed to extend toward a portion of a top surface of the lower molding material so as to not contact the inter-package connection unit.

8. The stack type semiconductor package of claim 7 , wherein the interconnection unit comprises a first interconnection unit which corresponds to a portion of the heat dissipation member formed on the lower semiconductor chip, and a second interconnection unit which corresponds to a portion of the heat dissipation member formed to extend to the portion of the top surface of the lower molding material.

9. The stack type semiconductor package of claim 1 , wherein the inter-package connection unit comprises a lower connection unit which is formed on the lower package substrate and an upper connection unit which is formed on the second upper lands of the upper package substrate,
wherein the upper connection unit and the interconnection unit have different heights.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jang-Woo
• Shim Jong-Bo
• Choi Kyoung-Sei

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/288

  characterised by arrangements for thermal management of the stacked chips · CPC title