Methods for pre-deposition treatment of a work-function metal layer

Patent metadata

Field	Value
Publication number	US-9978601-B2
Application number	US-201615192570-A
Country	US
Kind code	B2
Filing date	Jun 24, 2016
Priority date	Oct 20, 2015
Publication date	May 22, 2018
Grant date	May 22, 2018

Abstract

A method and structure for providing a pre-deposition treatment (e.g., of a work-function layer) to accomplish work function tuning. In various embodiments, a gate dielectric layer is formed over a substrate, and a work-function metal layer is deposited over the gate dielectric layer. In some embodiments, a first in-situ process including a pre-treatment process of the work-function metal layer is performed. By way of example, the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer. In some embodiments, after performing the first in-situ process, a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer is performed.

First claim

What is claimed is:

1. A method of semiconductor device fabrication, comprising:
forming a gate dielectric layer over a substrate;
depositing a work-function metal layer over the gate dielectric layer;
performing a first in-situ process including a pre-treatment process of the work-function metal layer, wherein the pre-treatment process removes an oxidized layer of the work-function metal layer to form a treated work-function metal layer; and
after performing the first in-situ process, performing a second in-situ process including a deposition process of another metal layer over the treated work-function metal layer.

2. The method of claim 1 , wherein the first in-situ process is performed in a first chamber of a processing system, and wherein the second in-situ process is performed in a second chamber of the processing system.

3. The method of claim 2 , wherein the first and second in-situ processes are performed while maintaining a vacuum condition of the processing system.

4. The method of claim 1 , wherein the pre-treatment process includes at least one of a Cl-based and a F-based metal precursor.

5. The method of claim 4 , wherein a flow rate of the precursor is between approximately 100 sccm and approximately 8000 sccm.

6. The method of claim 1 , wherein the work-function metal layer includes at least one of TiN, TaN, TiAlC, TiAl, TiSiN, TaSi, and TiAlN.

7. The method of claim 1 , wherein the work-function metal is deposited at a temperature from approximately 200 degrees Celsius to approximately 600 degrees Celsius.

8. The method of claim 1 , wherein the pre-treatment process is performed at a temperature from approximately 300 degrees Celsius to approximately 1000 degrees Celsius.

9. The method of claim 1 , wherein the work-function metal layer and the another metal layer are deposited by atomic layer deposition.

10. The method of claim 1 , wherein the another metal layer includes a TiAlC layer.

11. The method of claim 1 , further comprising performing a third in-situ process including depositing a TiN layer over the TiAlC layer.

12. The method of claim 1 , wherein the pre-treatment process shifts a band edge of the work-function metal layer.

13. A method of semiconductor device fabrication, comprising:
in a first chamber of an evacuated processing system, forming a gate dielectric layer over a substrate;
while maintaining a vacuum condition of the processing system, depositing a work-function metal layer over the gate dielectric layer in a second chamber of the evacuated processing system;
transferring the substrate to a third chamber of the evacuated processing system, while maintaining the vacuum condition of the evacuated processing system, and performing a pre-treatment process of the work-function metal layer in the third chamber, thereby forming a treated work-function metal layer; and
transferring the substrate to a fourth chamber of the evacuated processing system, while maintaining the vacuum condition of the evacuated processing system, and depositing a subsequent metal layer over the treated work-function metal layer in the fourth chamber.

14. The method of claim 13 , wherein the pre-treatment process removes an oxidized layer from a top surface of the work-function metal layer.

15. The method of claim 13 , wherein the work-function metal layer includes an N-type work function metal layer.

16. The method of claim 13 , wherein the subsequent metal layer includes a TiAlC layer.

17. The method of claim 16 , further comprising depositing a TiN layer over the TiAlC layer.

18. A method, comprising:
forming a high-K gate dielectric layer disposed over a fin-element;
depositing a work-function metal layer over the high-K gate dielectric layer;
performing a pre-treatment process of the work-function metal layer, wherein the pre-treatment process includes at least one of a Cl-based and a F-based metal precursor, and wherein the pre-treatment process removes an oxidized layer of the work-function metal layer, thereby forming a treated work-function metal layer; and
after performing the pre-treatment process, depositing a TiAlC layer over the treated work-function metal layer.

19. The method of claim 18 , wherein each of the forming the high-K gate dielectric layer, depositing the work-function metal layer, performing the pre-treatment process, and depositing the TiAlC layer are executed sequentially within a multi-chamber processing system, while maintaining a vacuum condition of the multi-chamber processing system.

20. The method of claim 18 , wherein the work-function metal layer includes at least one of TiN, TaN, TiAlC, TiAl, TiSiN, TaSi, and TiAlN.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Tsai Cheng-Yen
• Lee Hsin-Yi
• WU Chung-Chiang
• Lee Da-Yuan
• Chang Weng
• Tsai Ming-Hsing

Classifications

• H10P72/0454

  surrounding a central transfer chamber · CPC title

• H10P72/06

  Apparatus for monitoring, sorting, marking, testing or measuring · CPC title

• H10P14/40

  of conductive or resistive materials · CPC title

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/01318 Primary

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title