Pfet gate stack materials having improved threshold voltage, mobility and nbti performance

Patent metadata

Field	Value
Publication number	US-2016163603-A1
Application number	US-201414562991-A
Country	US
Kind code	A1
Filing date	Dec 8, 2014
Priority date	Dec 8, 2014
Publication date	Jun 9, 2016
Grant date	—

Abstract

A method of forming a transistor device includes forming an interfacial layer and a dielectric layer over a substrate; and forming a p-type field effect transistor (PFET) workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a lower titanium nitride (TiN) first layer and a second layer including one of titanium-aluminum-carbide (TiAlC) and tantalum-aluminum-carbide (TaAlC) formed on the lower TiN first layer.

First claim

What is claimed is:

1 . A method of forming a transistor device, the method comprising:
forming an interfacial layer and a dielectric layer over a substrate; and forming a p-type field effect transistor (PFET) workfunction metal layer over the dielectric layer, the workfunction metal layer comprising a lower titanium nitride (TiN) first layer and a second layer comprising one of titanium-aluminum-carbide (TiAlC) and tantalum-aluminum-carbide (TaAlC) formed on the lower TiN first layer.

2 . The method of claim 1 , wherein the lower TiN first layer is formed at thickness of about 2-8 angstroms (Å).

3 . The method of claim 1 , wherein the second layer is formed at thickness of about 12 Å or less.

4 . The method of claim 1 , further comprising forming an upper TiN third layer on the second layer, the upper TiN third layer being thicker than the lower TiN first layer.

5 . The method of claim 4 , wherein the upper TiN third layer is formed at a thickness of about 15-100 Å.

6 . The method of claim 1 , wherein the PFET workfunction metal layer is formed using atomic layer deposition (ALD).

7 . The method of claim 1 , further comprising forming a gate metal fill layer over the workfunction metal layer, thereby defining a gate stack.

8 . A method of forming a complementary metal oxide semiconductor (CMOS) device, the method comprising:
forming an interfacial layer and a dielectric layer over a substrate; and forming a p-type field effect transistor (PFET) workfunction metal layer over the dielectric layer in a PFET region, and forming an n-type field effect transistor (NFET) workfunction metal layer over the dielectric layer in an NFET region; wherein the PFET workfunction metal layer comprises a lower titanium nitride (TiN) first layer and a second layer comprising one of a titanium-aluminum-carbide (TiAlC) layer and a tantalum-aluminum-carbide (TaAlC) layer formed on the lower TiN first layer.

9 . The method of claim 8 , wherein the lower TiN first layer is formed at thickness of about 2-8 angstroms (Å).

10 . The method of claim 9 , wherein the second layer is formed at thickness of about 12 Å or less.

11 . The method of claim 10 , further comprising forming an upper TiN layer third on the second layer, the upper TiN third layer being thicker than the lower TiN first layer.

12 . The method of claim 11 , wherein the upper TiN third layer is formed at a thickness of about 15-100 Å.

13 . The method of claim 12 , wherein the PFET workfunction metal layer is formed using atomic layer deposition (ALD).

14 . The method of claim 13 , further comprising forming a gate metal fill layer over the PFET and NFET workfunction metal layers, thereby defining a gate stack.

15 . The method of claim 13 , further comprising:
initially forming the PFET workfunction metal layer in both the PFET region and the NFET region; removing the PFET workfunction metal layer from the NFET region; and forming the NFET workfunction metal layer over the dielectric layer in the NFET region, and over the PFET workfunction metal layer in the PFET region.

16 . The method of claim 13 , further comprising:
initially forming the NFET workfunction metal layer in both the NFET region and the PFET region; removing the NFET workfunction metal layer from the PFET region; and forming the PFET workfunction metal layer over the dielectric layer in the PFET region, and over the NFET workfunction metal layer in the NFET region.

17 . A transistor device, comprising:
an interfacial layer and a dielectric layer formed over a portion of a substrate; and a p-type field effect transistor (PFET) workfunction metal layer formed over the dielectric layer, the workfunction metal layer comprising a lower titanium nitride (TiN) first layer and a second layer comprising one of titanium-aluminum-carbide (TiAlC) and tantalum-aluminum-carbide (TaAlC) formed on the lower TiN first layer.

18 . The device of claim 17 , wherein the lower TiN first layer is formed at thickness of about 2-8 angstroms (Å).

19 . The device of claim 18 , wherein the second layer is formed at thickness of about 12 Å or less.

20 . The device of claim 19 , further comprising an upper TiN third layer formed on the second layer, the upper TiN third layer formed at a thickness of about 15-100 Å.

Assignees

• IBM

Inventors

• Bao Ruqiang
• Krishnan Siddarth
• Kwon Unoh
• Wong Keith Kwong Hon

Classifications

• H10D64/01342

  by deposition, e.g. evaporation, ALD or laser deposition (H10D64/01344 takes precedence) · CPC title

• H10D64/01336

  on single crystalline silicon, e.g. chemical oxidation using a liquid · CPC title

• H10D64/01318

  the conductor comprising a layer of alloy material, compound material or organic material contacting the insulator, e.g. TiN (comprising a layer of alloys of Si, Ge or C H10D64/01314) · CPC title

• H10D64/693

  the insulator comprising nitrogen, e.g. nitrides, oxynitrides or nitrogen-doped materials · CPC title

• H10D64/691

  comprising metallic compounds, e.g. metal oxides or metal silicates  (insulators comprising nitrogen H10D64/693) · CPC title