Method of manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-9972598-B2
Application number	US-201715640493-A
Country	US
Kind code	B2
Filing date	Jul 1, 2017
Priority date	Sep 16, 2016
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Reliability of a semiconductor device is improved.
A wire bonding step includes a step of exposing a wire and a pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of a ball portion, and forming a second hydroxyl layer on a surface of the pad electrode, a first bonding step of temporarily joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and after the first bonding step, a step of actually joining the ball portion to the pad electrode by performing a heat treatment on a semiconductor chip and a base material.

First claim

What is claimed is:

1. A method of manufacturing a semiconductor device, the method comprising the steps of:
(a) preparing a semiconductor chip having a pad electrode made of first copper, on a main surface of the semiconductor chip;
(b) preparing a base material having a chip mounting portion and a lead;
(c) after the step (b), mounting the semiconductor chip in the chip mounting portion; and
(d) after the step (c), coupling the pad electrode and the lead by using a wire which is made of second copper and has a ball portion and a wire portion,
wherein the step (d) includes the steps of
(d-1) exposing the wire and the pad electrode to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of the ball portion, and forming a second hydroxyl layer on a surface of the pad electrode,
(d-2) a first bonding step of joining the ball portion to the pad electrode through the first hydroxyl layer and the second hydroxyl layer, and
(d-3) after the first bonding step, joining the ball portion to the pad electrode by performing a heat treatment on the semiconductor chip and the base material.

2. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the reducing gas atmosphere contains nitrogen and hydrogen.

3. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the second hydroxyl layer is formed on a surface of an oxidized layer formed on a surface of the pad electrode.

4. The method of manufacturing a semiconductor device according to claim 3 ,
wherein after the step (d-2), a first bonding layer formed by first hydrogen bond and first ionic bond is formed between the ball portion and the pad electrode.

5. The method of manufacturing a semiconductor device according to claim 4 ,
wherein the step (d-2) is performed in 130° C.-250° C.

6. The method of manufacturing a semiconductor device according to claim 4 ,
wherein the first ionic bond included in the first bonding layer is formed of a first copper atom of the first copper, an oxygen atom of the oxidized layer, and a second copper atom of the second copper.

7. The method of manufacturing a semiconductor device according to claim 6 ,
wherein after the step (d-3), a first metallic bond layer made of the first copper atoms and the second copper atoms is formed between the pad electrode and the ball portion.

8. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the step (d-3) is performed in an inert gas atmosphere.

9. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the step (d-3) is performed in a low-vacuum atmosphere of 10 Mpa or higher.

10. The method of manufacturing a semiconductor device according to claim 1 ,
wherein the step (d-1) further includes the steps of exposing the lead to the reducing gas atmosphere, forming a third hydroxyl layer on a surface of the wire portion, and forming a fourth hydroxyl layer on a surface of the lead, and
wherein the method further includes
(d-4) between the step (d-2) and the step (d-3), a second bonding step of bonding the wire portion to the lead through the third hydroxyl layer and the fourth hydroxyl layer.

11. The method of manufacturing a semiconductor device according to claim 10 ,
wherein after the step (d-2), a second bonding layer formed by second hydrogen bond and second ionic bond is formed between the wire portion and the lead made of third copper.

12. The method of manufacturing a semiconductor device according to claim 11 ,
wherein after the step (d-3), a second metallic bond layer made of second copper atoms of the second copper and third copper atoms of the third copper is formed between the wire portion and the lead.

13. The method of manufacturing a semiconductor device according to claim 1 , further comprising the step of:
(e) between the step (c) and the step (d), performing plasma cleaning processing on a surface of the pad electrode.

14. The method of manufacturing a semiconductor device according to claim 1 , further comprising the step of:
(f) after the step (d), sealing the semiconductor chip, the lead, and the wire with a resin.

15. A method of manufacturing a semiconductor device, the method comprising the steps of:
(a) preparing a semiconductor chip having a plurality of pad electrodes made of first copper, on a main surface of the semiconductor chip;
(b) preparing a base material having a chip mounting portion and a plurality of leads made of second copper;
(c) mounting the semiconductor chip in the chip mounting portion; and
(d) sequentially coupling the pad electrodes and the leads together by using a wire which is made of third copper and has a ball portion and a wire portion,
wherein the step (d) includes the steps of
(d-1) exposing the wire, the pad electrodes, and the leads to a reducing gas atmosphere, forming a first hydroxyl layer on a surface of the ball portion, forming a second hydroxyl layer on surfaces of the pad electrodes, forming a third hydroxyl layer on a surface of the wire portion, and forming a fourth hydroxyl layer on surfaces of the leads,
(d-2) a first bonding step of joining the ball portion to one of the pad electrodes through the first hydroxyl layer and the second hydroxyl layer,
(d-3) a second bonding step of bonding the wire portion to one of the leads through the third hydroxyl layer and the fourth hydroxyl layer,
(d-4) repeatedly performing the first bonding step and the second bonding step and sequentially bonding the pad electrodes and the leads together, and
(d-5) after the step (d-4), performing a heat treatment on the semiconductor chip and the base material, joining the ball portion to one of the pad electrodes, and joining the wire portion to one of the leads.

16. The method of manufacturing a semiconductor device according to claim 15 ,
wherein after the step (d-2), a first bonding layer famed by first hydrogen bond and first ionic bond is formed between the ball portion and the one of the pad electrodes, and
wherein after the step (d-3), a second bonding layer formed by second hydrogen bond and second ionic bond is formed between the wire portion and the one of the leads.

17. The method of manufacturing a semiconductor device according to claim 15 ,
wherein after the step (d-4), a first metallic bond layer made of first copper atoms of the first copper and third copper atoms of the third copper is formed between the pad electrode and the ball portion, and a second metallic bond layer made of second copper atoms of the second copper and the third copper atoms is formed between the lead and the wire portion.

18. The method of manufacturing a semiconductor device according to claim 15 ,
wherein the step (d-5) is performed in a state which the base material where the semiconductor chip is mounted is put in a chamber.

19. The method of manufacturing a semiconductor device according to claim 15 ,
wherein in the step (d-1), a guide hole of a capillary is filled with the reducing gas atmosphere, and the fourth hydroxyl layer is formed by inserting the wire into the guide hole.

Assignees

• Renesas Electronics Corp

Inventors

• Yagyu Yuki

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W80/327

  characterised by the direct bonding of insulating parts, e.g. of silicon oxide layers · CPC title

• H10W74/111

  the semiconductor body being completely enclosed · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title