Picture frame stiffeners for microelectronic packages

Patent metadata

Field	Value
Publication number	US-9502368-B2
Application number	US-201414571623-A
Country	US
Kind code	B2
Filing date	Dec 16, 2014
Priority date	Dec 16, 2014
Publication date	Nov 22, 2016
Grant date	Nov 22, 2016

Abstract

A microelectronic package may be formed with a picture frame stiffener surrounding a microelectronic die for reducing warpage of the microelectronic package. An embodiment for fabricating such a microelectronic package may include forming a microelectronic die having an active surface and an opposing back surface, wherein the microelectronic die active surface may be attached to a microelectronic substrate. A picture frame stiffener having an opening therethrough may be formed and placed on a release film, wherein a mold material may be deposited over the picture frame stiffener and the release film. The microelectronic die may be inserted into the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening. The release film may be removed and a portion of the mold material extending over the microelectronic die back surface may then be removed to form the microelectronic package.

First claim

What is claimed is:

1. A microelectronic package, comprising:
a microelectronic die having an active surface and a back surface, wherein the microelectronic die is electrically connected to a microelectronic substrate through interconnects extending between the microelectronic die active surface and a first surface of the microelectronic substrate;
a mold material abutting the microelectronic device and the microelectronic substrate first surface; and
a picture frame stiffener having a opening therethrough, wherein the picture frame stiffener is at least partially embedded in the mold material, wherein at least a portion of the microelectronic die extends into the picture frame opening, and wherein the mold material does not extend over the microelectronic die back surface.

2. The microelectronic package of claim 1 , wherein the picture frame stiffener comprises a layered structure having at least two material layers having differing coefficients of thermal expansion.

3. The microelectronic package of claim 1 , wherein the picture frame stiffener comprises a base portion and a rigidity projection extending from a first surface of the base portion.

4. The microelectronic package of claim 3 , wherein the rigidity projection is integral to the base portion.

5. The microelectronic package of claim 3 , wherein the rigidity projection and the base portion comprise differing materials having differing coefficients of thermal expansion.

6. The microelectronic package of claim 1 , further including at least one through mold interconnect extending from a corresponding through mold interconnect bond pad on the microelectronic substrate first surface.

7. The microelectronic package of claim 1 , wherein the picture frame stiffener is electrically conductive and includes at least one electrically conductive projection extending through the mold material and electrically contacting a corresponding stiffener connection bond pad on the microelectronic substrate first surface.

8. The microelectronic package of claim 1 , wherein the picture frame stiffener comprises a dielectric material having a first surface and a second surface, and at least one conductive via extending from the dielectric material first surface to the dielectric material second surface.

9. The microelectronic package of claim 8 , further including at least one through mold interconnect extending from a corresponding through mold interconnect bond pad on the microelectronic substrate first surface, wherein the at least one through mold interconnect is in electrical contact with the at least one conductive via of the picture frame stiffener.

10. The microelectronic package of claim 9 , further including a secondary microelectronic package in electrical contact with the at least one conductive via of the picture frame stiffener.

11. The microelectronic package of claim 10 , further including a secondary microelectronic die electrically connected to through-silicon vias extending into the microelectronic die from the microelectronic die back surface.

Assignees

• Intel Corp

Inventors

• Tomita Yoshihiro
• Kubota Jiro
• Karhade Omkar G
• Liff Shawna M
• Ichikawa Kinya
• Deshpande Nitin A

Classifications

• H10W90/732

  between stacked chips · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/722

  between stacked chips · CPC title

• H10W90/297

  characterised by the through-semiconductor vias [TSVs] in the stacked chips · CPC title

• H10W74/142

  the encapsulations exposing the passive side of the semiconductor body · CPC title