Mitigation of far-end crosstalk induced by routing and out-of-plane interconnects

Patent metadata

Field	Value
Publication number	US-9515031-B2
Application number	US-201113976447-A
Country	US
Kind code	B2
Filing date	Dec 29, 2011
Priority date	Dec 29, 2011
Publication date	Dec 6, 2016
Grant date	Dec 6, 2016

Abstract

In accordance with one aspect of the present description, a transmission line such as a microstrip or stripline transmission line, has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk (FEXT) induced by inductive coupling between the transmission line and an adjacent transmission line, and also far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line. In another aspect of the present description, a microstrip transmission line may have multiple stubby line sections having different resistances and impedances to more gradually transition from to the typically low impedance characteristics of vertical interconnects such as the PTH vias and socket connectors. Other aspects are described.

First claim

What is claimed is:

1. A system: comprising:
a printed circuit board having signal line conductors;
a processor disposed over the printed circuit board;
a memory electrically connected to the processor;
a video controller electrically connected to the processor;
a package substrate disposed over the printed circuit board such that the substrate is vertically displaced relative to the printed circuit board;
a die supported by the substrate and having an integrated circuit;
a plurality of transmission lines supported by the substrate and electrically connected to the integrated circuit of the die at a near end of the transmission lines; and
a plurality of vertical electrical interconnects electrically connected to the transmission lines at a far end of the transmission lines and adapted to vertically and electrically connect the transmission lines to signal line conductors of the printed circuit board,
wherein each transmission line has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk induced by inductive coupling between the transmission line and an adjacent transmission line, and far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line, and
wherein each transmission line has first and second impedance stepping sections between the near end and far end of the transmission line, each impedance stepping section having a plurality of stub-shaped projections wherein the first impedance stepping section has a higher capacitance and a lower resistance compared to the second impedance stepping section which is positioned between the first impedance stepping section and the near end of the transmission line.

2. The system of claim 1 wherein each vertical electrical interconnect is a pin disposed in and passing vertically through the package substrate.

3. The system of claim 2 wherein the printed circuit board has a socket having a plurality of socket pin receptors, and wherein each pin of the plurality of vertical electrical interconnects is a socket pin adapted to be received by a socket receptor.

4. The system of claim 3 wherein the stub-shaped projections of each transmission line are further adapted to compensate simultaneously for far-end crosstalk induced by inductive coupling between the socket pin receptor coupled to the socket pin electrically connected to the far end of the transmission line, and an adjacent socket pin receptor electrically connected to the socket pin electrically connected to the far end of the adjacent transmission line.

5. The system of claim 1 wherein a signal line conductor of the printed circuit board has a far end crosstalk-induced voltage V f in response to an input voltage of V i applied to an input of a transmission line of the plurality of transmission lines of the package substrate, wherein V f is expressed as

V
f

⁡

(
t
)

=

t
f

2

⁢

(

C
m

C
T

-

L
m

L
s

)

⁢

ⅆ

V
i

⁡

(

t
-

t
f

)

ⅆ
t

,

where t f is the time of flight, C T =C m +C S , and C m , C S , L m and L S represent the combined mutual capacitance, combined self capacitance, combined mutual inductance and combined self inductance, respectively, between a transmission line and an adjacent transmission line, and between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line, and wherein the stub-shaped projections provide additional self and mutual capacitances to increase the ratio C m /C T as compared to the ratio L m /L S , to reduce the far end crosstalk-induced voltage V f .

6. The system of claim 5 wherein the stub-shaped projections provide additional self and mutual capacitances to increase the ratio C m /C T to substantially equal the ratio L m /L S , to reduce the far end crosstalk-induced voltage V f substantially to zero.

7. The system of claim 1 wherein the transmission lines include microstrip transmission lines.

8. The system of claim 1 wherein the transmission lines include stripline transmission lines.

9. The system of claim 1 wherein each vertical electrical interconnect includes a through-hole via comprising a through hole formed in and passing through the package substrate, and a layer of conductive metal plating the surface of the through hole.

10. A package for use with a printed circuit board having signal line conductors, comprising:
a substrate adapted to be disposed over the printed circuit board such that the substrate is vertically displaced relative to the printed circuit board; a die supported by the substrate and having an integrated circuit;
a plurality of transmission lines supported by the substrate and electrically connected to the integrated circuit of the die at a near end of the transmission lines;
a plurality of vertical electrical interconnects electrically connected to the transmission lines at a far end of the transmission lines and adapted to vertically and electrically connect the transmission lines to signal line conductors of the printed circuit board, wherein each transmission line has stub-shaped projections adapted to compensate simultaneously for both far-end crosstalk induced by inductive coupling between the transmission line and an adjacent transmission line, and far-end crosstalk induced by inductive coupling between the vertical electrical interconnect at the far end of the transmission line and an adjacent vertical electrical interconnect electrically connected to the adjacent transmission line,
wherein each transmission li

Assignees

• Altunyurt Nevin
• Aygun Kemal
• Doran Kevin J
• Mekonnen Yidnekachew S
• Intel Corp

Inventors

• Altunyurt Nevin
• Aygun Kemal
• Doran Kevin J
• Mekonnen Yidnekachew S

Classifications

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W70/635

  Through-vias · CPC title

• H10W44/216

  Waveguides, e.g. strip lines · CPC title

• H10W70/65

  Shapes or dispositions of interconnections · CPC title

• H10W44/00

  Electrical arrangements for controlling or matching impedance · CPC title