Semiconductor chip package comprising side wall marking

Patent metadata

Field	Value
Publication number	US-9972576-B2
Application number	US-201615361034-A
Country	US
Kind code	B2
Filing date	Nov 24, 2016
Priority date	Nov 25, 2015
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.

First claim

The invention claimed is:

1. A semiconductor chip package, comprising:
a semiconductor chip;
an encapsulation body encapsulating the semiconductor chip;
a chip pad;
wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side faces have a smaller surface area than the main faces, respectively;
wherein a marking is provided on at least one of the side faces; and
wherein the semiconductor chip is disposed on the chip pad and a first main face of the chip pad remote from the semiconductor chip is at least partially exposed.

2. The semiconductor chip package according to claim 1 , wherein
the marking comprises an information about the semiconductor chip.

3. The semiconductor chip package according to claim 2 , wherein
the information about the semiconductor chip comprises a label or a code, wherein the label or the code characterizes the type or kind of the semiconductor chip.

4. The semiconductor chip package according to claim 2 , wherein
the information comprises one or more of the following group of information elements:
type or kind of the semiconductor chip, current class, voltage class, power class, polarity, blocking capability, fabrication date.

5. The semiconductor chip package according to claim 1 , wherein
the marking comprises an information about the semiconductor chip package or the encapsulation body.

6. The semiconductor chip package according to claim 5 , wherein
the information comprises a label or a code, wherein the label or the code characterizes the type or the kind of the semiconductor chip package or the encapsulation body.

7. The semiconductor chip package according to claim 1 , wherein
the marking comprises at least alphanumeric character or a combination of alphanumeric characters.

8. The semiconductor chip package according to claim 1 , wherein
the marking comprises a portion comprising the company logo or company mark of the manufacturer of the semiconductor chip package.

9. The semiconductor chip package according to claim 1 , further comprising:
a first pair of first opposing side faces of a first surface area; and
a second pair of second opposing side faces of a second surface area, wherein
the first surface area is greater than the second surface area and the marking is provided on one of the first opposing side faces.

10. The semiconductor chip package according to claim 1 , further comprising
four side faces; and
electrical contact elements connected with the semiconductor chip and extending outwardly, wherein
the electrical contact elements extend through two opposing side faces and the marking is provided on one of the other two opposing side faces.

11. The semiconductor chip package according to claim 10 , wherein
the electrical contact elements extend exclusively through two opposing side faces which have the smallest surface areas from all side faces.

12. The semiconductor chip package according to claim 1 , wherein
the first main face of the chip pad is exposed at one of the two opposing main faces of the encapsulation body.

13. The semiconductor chip package according to claim 1 , wherein
the semiconductor chip package is configured as a surface-mount device.

14. The semiconductor chip package according to claim 13 , wherein
the semiconductor chip package is one of the type TO252 or TO263.

15. An electronic device package, comprising:
an electronic device;
an encapsulation body encapsulating the electronic device;
a leadframe, the leadframe comprising electrical contact elements and a chip pad;
wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side faces have a smaller surface area than the main faces, respectively;
wherein a marking is provided on at least one of the side faces; and
wherein the electronic device is disposed on the chip pad and a first main face of the chip pad remote from the electronic device is at least partially exposed.

16. The electronic device package according to claim 15 , wherein
the electronic device comprises a semiconductor chip, the semiconductor chip comprising one or more of a transistor, a metal-oxide semiconductor transistor, a vertical transistor, an insulated gate bipolar transistor, and a power transistor.

Assignees

• Infineon Technologies Austria Ag

Inventors

• Otremba Ralf
• Lee Teck Sim
• Hud Amirul Afiq
• Schnoy Fabian
• Grawert Felix
• Kirchner Uwe
• Schmoelzer Bernd
• Stueckler Franz

Classifications

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W90/736

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5363

  the connected ends being wedge-shaped · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title