Adder circuitry for very large integers
US-10873332-B2 · Dec 22, 2020 · US
in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination · Cooperative Patent Classification (CPC)
Computing, optics, measurement, and control technologies.
Related technology areas
Mapped technology topics for this CPC code.
| Metric | Value |
|---|---|
| CPC code | G06F7/505 |
| Official title | in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination |
| Display label | in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination |
| Total patents | 146 |
Filing trend
Year-over-year patent counts classified under this CPC code.
Filing activity over the last five years is stable.
| Year | Patents |
|---|---|
| 2015 | 2 |
| 2016 | 4 |
| 2017 | 4 |
| 2018 | 11 |
| 2019 | 17 |
| 2020 | 23 |
| 2021 | 13 |
| 2022 | 18 |
| 2023 | 28 |
| 2024 | 15 |
| 2025 | 11 |
Representative patents
Representative publications under this CPC code from precomputed stats, or recent filings when stats are unavailable.
Fast binary counters based on symmetric stacking and methods for same
US-2020394017-A1 · Dec 17, 2020 · US
Data Compressor Logic Circuit
US-2020389181-A1 · Dec 10, 2020 · US
Fixed-point and floating-point arithmetic operator circuits in specialized processing blocks
US-10838695-B2 · Nov 17, 2020 · US
Concurrent multi-bit adder
US-10824394-B2 · Nov 3, 2020 · US
Oblivious carry runway registers for performing piecewise additions
US-2020310760-A1 · Oct 1, 2020 · US
Measurement Based Uncomputation for Quantum Circuit Optimization
US-2020311594-A1 · Oct 1, 2020 · US
Quantum circuit optimization using windowed quantum arithmetic
US-2020311592-A1 · Oct 1, 2020 · US
Surface code computations using auto-ccz quantum states
US-2020311593-A1 · Oct 1, 2020 · US
Data compressor logic circuit
US-10756753-B2 · Aug 25, 2020 · US
Methods of manufacturing semiconductor devices by etching active fins using etching masks
US-2020211907-A1 · Jul 2, 2020 · US
Binary parallel adder and multiplier
US-2020210146-A1 · Jul 2, 2020 · US
Massively parallel neural inference computing elements
US-2020202205-A1 · Jun 25, 2020 · US
Processing apparatus and method of processing add operation therein
US-2020159495-A1 · May 21, 2020 · US
Data Compressor Logic Circuit
US-2020136643-A1 · Apr 30, 2020 · US
Processing apparatus and processing method
US-2020117976-A1 · Apr 16, 2020 · US
Massively parallel neural inference computing elements
US-10621489-B2 · Apr 14, 2020 · US
Methods of manufacturing semiconductor devices by etching active fins using etching masks
US-10615080-B2 · Apr 7, 2020 · US
Processing apparatus and processing method
US-2020097794-A1 · Mar 26, 2020 · US
Processing apparatus and processing method
US-2020097792-A1 · Mar 26, 2020 · US
Frequently asked questions
Answers are generated from the same data shown on this page.
- What is CPC G06F7/505?
- CPC G06F7/505 is the Cooperative Patent Classification code for “in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination.”
- How many patents are filed under CPC G06F7/505 (in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination)?
- Our database includes 146 publications tagged with this CPC code.
- Is patent activity under CPC G06F7/505 growing?
- Publication counts under this code: 15 in 2024 vs 11 in 2025 (latest complete years).