Package for image sensor with outer and inner frames

Patent metadata

Field	Value
Publication number	US-9966401-B2
Application number	US-201615049002-A
Country	US
Kind code	B2
Filing date	Feb 19, 2016
Priority date	Mar 4, 2015
Publication date	May 8, 2018
Grant date	May 8, 2018

Abstract

A semiconductor package according to the inventive concepts includes an image sensor chip mounted on a substrate, a first holder disposed on an edge area of the image sensor chip, a second holder disposed laterally spaced apart from the image sensor chip on an edge area of the substrate, a molding part provided in a gap region between the first holder and the second holder on the substrate, and a transparent cover disposed on the first holder and the molding part.

First claim

What is claimed is:

1. A semiconductor package comprising:
a substrate;
an image sensor chip mounted on the substrate;
a first holder disposed on an edge area of the image sensor chip;
a second holder disposed laterally spaced apart from the image sensor chip on an edge area of the substrate;
a molding part provided in a gap region between the first holder and the second holder on the substrate;
an adhesion part disposed on the first holder and the molding part; and
a transparent cover disposed on the adhesion part,
wherein the first holder has a closed loop shape,
wherein the second holder has a closed loop shape,
wherein a part of the first holder is separated from the second holder, and
wherein the adhesion part is in direct contact with the molding part.

2. The semiconductor package of claim 1 , further comprising:
a connection holder connecting the first holder to the second holder on the substrate,
wherein the first holder, the second holder, and the connection holder include the same material.

3. The semiconductor package of claim 2 ,
wherein the connection holder extends in a direction diagonal to a sidewall of the image sensor chip and connects a corner of the first holder to a corner of the second holder.

4. The semiconductor package of claim 2 , further comprising:
bonding wires disposed on the substrate to electrically connect the image sensor chip to the substrate,
wherein the bonding wires are laterally spaced apart from the connection holder.

5. The semiconductor package of claim 1 ,
wherein the adhesion part is disposed between a top surface of the first holder and a bottom surface of the transparent cover and between a top surface of the molding part and the bottom surface of the transparent cover.

6. The semiconductor package of claim 5 ,
wherein the adhesion part includes a different material from the molding part.

7. The semiconductor package of claim 5 ,
wherein the top surface of the molding part is disposed at the same level as or a lower level than the top surface of the first holder, and
wherein a top surface of the adhesion part disposed on the molding part is disposed at substantially the same level as a top surface of the adhesion part disposed on the first holder.

8. The semiconductor package of claim 1 ,
wherein the transparent cover covers a top surface of the second holder.

9. The semiconductor package of claim 1 ,
wherein the transparent cover is disposed on an inner sidewall of the second holder, and
wherein a top surface of the transparent cover is disposed at substantially a same level as or a higher level than a top surface of the second holder.

10. A semiconductor package comprising:
a substrate;
an image sensor chip mounted on the substrate;
a holder provided on the substrate, the holder including a first holder, a second holder, and a connection holder, the first holder disposed on the image sensor chip, the second holder laterally spaced apart from the image sensor chip, and the connection holder connecting the first holder to the second holder;
a molding part filling a gap region between the first and second holders on the substrate;
a transparent cover disposed on the first holder and the molding part; and
an adhesion part disposed between the molding part and the transparent cover,
wherein the adhesion part is in direct contact with the molding part.

11. The semiconductor package of claim 10 , further comprising:
bonding wires electrically connecting the image sensor chip to the substrate on the substrate,
wherein the bonding wires do not overlap with the connection holder when viewed in plan view.

12. The semiconductor package of claim 10 ,
wherein the adhesion part is further disposed between the holder and the transparent cover,
wherein the adhesion part includes a photo-curable polymer or a photo/heat dual curable polymer, and
wherein the molding part includes a thermosetting polymer.

13. The semiconductor package of claim 12 ,
wherein a top surface of the molding part is disposed at a lower level than a top surface of the holder, and
wherein a top surface of the adhesion part disposed on the molding part is disposed at substantially the same level as a top surface of the adhesion part disposed on the first holder of the holder.

14. The semiconductor package of claim 10 ,
wherein a top surface of the second holder is disposed at a higher level than a top surface of the first holder and is disposed at substantially the same level as or a lower level than a top surface of the transparent cover.

15. The semiconductor package of claim 10 , further comprising:
a first adhesive film disposed between the first holder and the image sensor chip; and
a second adhesive film disposed between the second holder and the substrate.

16. A semiconductor package comprising:
a substrate;
an image sensor chip mounted on the substrate;
a first holder disposed on an edge area of the image sensor chip to surround micro-lenses of the image sensor chip;
a second holder spaced apart from the image sensor chip and disposed on an edge area of the substrate to surround the image sensor chip;
a molding part disposed in a gap region between the first holder and the second holder on the substrate;
an adhesion part disposed on the first holder and the molding part; and
a transparent cover disposed on the adhesion part to form an air gap defined by a bottom surface of the transparent cover, side walls of the first holder, and a top surface of the image sensor chip,
wherein the air gap is sealed by the adhesion part, and
wherein the adhesion part is in direct contact with the molding part.

17. The semiconductor package of claim 16 ,
wherein a top surface of the adhesion part disposed on the first holder and a top surface of the adhesion part disposed on the molding part are at substantially a same level.

18. The semiconductor package of claim 17 ,
wherein a top surface of the transparent cover is disposed at a level that is substantially the same as a level of a top surface of the second holder or at a level that is different from a level of a top of the second holder; and
wherein the adhesion part is further disposed between a portion of side walls of the second holder and a sidewall of the transparent cover.

19. The semiconductor package of claim 17 ,
wherein the adhesion part is further disposed on the second holder, and a top surface of the first holder and a top surface of the second holder are disposed at substantially a same level.

20. The semiconductor package of claim 16 , further comprises:
a connection holder to connect the first holder and the second holder,
wherein the connection holder extends in a direction diagonal to a sidewall of the image sensor chip and connects a corner of the first holder to a corner of the second holder, and
wherein the connection holder covers the sidewall of the image sensor chip and a portion of the top surface of the image sensor chip adjacent to the sidewall.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jun Hyunsu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/932

  Plan-view shape, i.e. in top view · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title