Semiconductor Package and Method for Manufacturing the Same

Patent metadata

Field	Value
Publication number	US-2016005778-A1
Application number	US-201514730348-A
Country	US
Kind code	A1
Filing date	Jun 4, 2015
Priority date	Jul 7, 2014
Publication date	Jan 7, 2016
Grant date	—

Abstract

Provided is a semiconductor package including: a substrate; an image sensor chip disposed on the substrate and including a first surface that faces the substrate and a second surface that is opposed to the first surface; an adhesion layer interposed between the substrate and the image sensor chip; and a first cavity surrounded by the first surface, an upper surface of the substrate and a side surface of the adhesion layer. The first surface includes a first central portion and a first edge portion, the adhesion layer includes a first adhesion part directly contacting the first central portion and a second adhesion part directly contacting the substrate, and the first adhesion part has an area corresponding to about 5% to about 50% of an area of the first surface.

First claim

What is claimed is:

1 . A semiconductor package comprising:
a substrate; an image sensor chip disposed on the substrate and including a first surface that faces the substrate and a second surface that is opposed to the first surface; an adhesion layer interposed between the substrate and the image sensor chip; and a first cavity surrounded by the first surface of the image sensor chip, an upper surface of the substrate and a side surface of the adhesion layer, wherein the first surface of the image sensor chip comprises a first central portion and a first edge portion, and the adhesion layer comprises a first adhesion portion directly contacting the first central portion and a second adhesion portion directly contacting the upper surface of the substrate, wherein the first adhesion portion has an area of about 5% to about 50% of an area of the first surface of the image sensor chip.

2 . The semiconductor package of claim 1 , wherein the substrate comprises a second central portion and a second edge portion, and wherein the second adhesion portion directly contacts the second central portion.

3 . The semiconductor package of claim 1 , wherein the adhesion layer has a thickness of about 1 μm to about 80 μm, and wherein the second adhesion portion has an area greater than that of the first adhesion portion.

4 . The semiconductor package of claim 1 , wherein the first adhesion portion is spaced apart from the first edge portion of the image sensor chip, and wherein the first adhesion portion has a circular shape on the image sensor chip first surface.

5 . The semiconductor package of claim 1 , wherein the adhesion layer has a modulus of about 2.7 MPa to about 4.2 MPa at a temperature of about −60° C. to about 230° C.

6 . The semiconductor package of claim 1 , wherein the substrate is a plastic substrate.

7 . The semiconductor package of claim 6 , wherein the plastic substrate is a printed circuit board (PCB).

8 . The semiconductor package of claim 1 , wherein the substrate has a thermal expansion coefficient of about 13 ppm/° C. or less at room temperature.

9 . The semiconductor package of claim 1 , wherein the image sensor has a warpage of about 10 μm or less.

10 . The semiconductor package of claim 1 , further comprising:
a holder having an upper surface spaced apart from the second surface of the image sensor chip; and a transparent substrate disposed so as to be adjacent the upper surface of the holder.

11 . The semiconductor package of claim 10 , further comprising a second cavity surrounded by the transparent substrate, the holder and the image sensor chip.

12 . The semiconductor package of claim 10 , wherein the substrate, the image sensor chip, the adhesion layer, the holder and the transparent substrate are comprised of materials having different material characteristics.

13 . The semiconductor package of claim 1 , further comprising:
a transparent substrate on the image sensor chip; and a mold film covering a side surface of the transparent substrate and a side surface of the image sensor chip, wherein the first cavity is surrounded by the first surface of the image sensor chip, the upper surface of the substrate, the side surface of the adhesion layer, and the mold film.

14 . A semiconductor package comprising:
a substrate; an image sensor chip disposed on the substrate and including a first surface that faces the substrate and a second surface that is opposite the first surface; and an adhesion layer interposed between the substrate and the image sensor chip, wherein the adhesion layer comprises a first adhesion portion directly contacting the first surface of the image sensor chip, wherein an area of the first adhesion portion is about 5% to about 50% of an area of the first surface, and wherein the adhesion layer has an elastic modulus of about 2.7 MPa to about 4.2 MPa at a temperature of about −60° C. to about 230° C.

15 . The semiconductor package of claim 14 , wherein the substrate has a thermal expansion coefficient of about 13 ppm/° C. or less at room temperature.

16 . A semiconductor package comprising:
a substrate comprising a printed circuit board (PCB), the substrate comprising first and second opposing sides; an image sensor chip on the substrate, the image sensor chip comprising a first side that faces the substrate and a second side opposing the first side; and an adhesion layer between the substrate and the image sensor chip; wherein the first side of the image sensor chip comprises a first central portion and a first edge portion, and wherein the adhesion layer comprises: a first adhesion surface directly contacting the first central portion and spaced apart from the first edge portion; and a second adhesion surface directly contacting the first side of the substrate.

17 . The semiconductor package of claim 16 , further comprising:
a holding member on the substrate, the holding member comprising an upper surface spaced apart from the second side of the image sensor chip; and a transparent substrate on the upper surface of the holding member.

18 . The semiconductor package of claim 16 , further comprising:
a transparent substrate on the image sensor chip; and a mold film covering at least a portion of a side surface of the transparent substrate and a side surface of the image sensor chip, wherein the first side of the image sensor chip, the first side of the substrate, the side surface of the adhesion layer, and the mold film define a first cavity.

19 . The semiconductor package of claim 18 , further comprising a microlens array in a recessed region defined in the second side of the image sensor chip.

20 . The semiconductor package of claim 16 , wherein the first adhesion surface has an area of about 5% to about 50% of an area of the first side of the image sensor chip.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jun Hyunsu

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/734

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/5449

  not being orthogonal to a side surface of the chip, e.g. fan-out arrangements · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title